This paper presents a comprehensive review of various techniques employed to enhance the low voltage ride through (LVRT) capability of the fixed-speed induction generators (FSIGs)-based wind turbines (WTs), which has a non-negligible 20% contribution of the existing wind energy in the world. As the FSIG-based WT system is directly connected to the grid with no power electronic interfaces, terminal voltage or reactive power output may not be precisely controlled. Thus, various LVRT strategies based on installation of the additional supporting technologies have been proposed in the literature. Although the various individual technologies are well documented, a comparative study of existing approaches has not been reported so far. This paper attempts to fill this void by providing a comprehensive analysis of these LVRT methods for FSIG-based WTs in terms of dynamic performance, controller complexity, and economic feasibility. A novel feature of this paper is to categorize LVRT capability enhancement approaches into three main groups depending on the connection configuration: series, shunt, and series-shunt (hybrid) connections and then discuss their advantages and limitations in detail. For verification purposes, several simulations are presented in MATLAB software to demonstrate and compare the reviewed LVRT schemes. Based on the simulated results, series connection dynamic voltage restorer (DVR) and shunt connection static synchronous compensators (STATCOM) are the highly efficient LVRT capability enhancement approaches.

Synchrophasor devices guarantee situation awareness for real-time monitoring and operational visibility of the smart grid. With their widespread implementation, significant challenges have emerged, especially in communication, data quality and cybersecurity. The existing literature treats these challenges as separate problems, when in reality, they have a complex interplay. This paper conducts a comprehensive review of quality and cybersecurity challenges for synchrophasors, and identifies the interdependencies between them. It also summarizes different methods used to evaluate the dependency and surveys how quality checking methods can be used to detect potential cyberattacks. In doing so, this paper serves as a starting point for researchers entering the fields of synchrophasor data analytics and security.

This paper presents a positive approach in an optimized design of a combinatory unified power-quality conditioner (UPQC) and superconducting fault current limiters (SFCLs). This is based on a normalized simulated annealing algorithm compared with analytic hierarchy process objective optimization. The optimization algorithm for simultaneous optimization computes and produces three-dimensional alignments in Pareto front at the end of the optimization run. The results show that the SFCL can reduce the volt-ampere rating of the UPQC by limiting the fault current, thereby reducing the cost of UPQC installation. The aforementioned algorithm requires advanced numerical techniques for simulation studies by PSCAD/EMTDC on a sample distribution system for determining a global optimal combination of UPQC and SFCL by considering individual parameters and accounting for the constraints, which is the main motivation of this paper. This will result in a more thorough knowledge of "scaling factors" and the system quality mechanism which will enable the most efficient systems from the viewpoints of cost cutting, energy savings, and downsizing.Index Terms-Analytic hierarchy process, multiobjective decision making, power quality (PQ), simulated annealing, superconducting fault current limiter, unified power-quality conditioner (UPQC).

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This paper proposes an algorithm for the calculation of short circuit forces on the high current busbars of electric arc furnace (EAF) transformers based on the method of images using an analytical solution for the electromagnetic force between two adjacent current carrying rectangular conductor. The theory of images is used to account for the impact of the tank walls on the short circuit forces on the busbars. The proposed method uses an iterative algorithm and increases the number of image layers to achieve the desired accuracy. A 30 MVA EAF transformer is investigated as a case study and the results are compared to 2D finite element analysis (FEA). ANSYS software is used for the FEA. The proposed algorithm converges very fast, so that only in its first iteration, the convergence error is less than 0.2%. The comparisons show that the short circuit force calculations using the proposed method, conform to the 2D FEA results. However, the short-circuit calculation time using the proposed method is about 20 times faster than the 2D FEA with the same relative error. Therefore it can be used as a faster alternative for the FEA. The proposed method is characterized by fast convergence, simple calculations and high precision.