2011
DOI: 10.1109/tpwrd.2011.2111390
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Optimization Scheme in Combinatorial UPQC and SFCL Using Normalized Simulated Annealing

Abstract: This paper presents a positive approach in an optimized design of a combinatory unified power-quality conditioner (UPQC) and superconducting fault current limiters (SFCLs). This is based on a normalized simulated annealing algorithm compared with analytic hierarchy process objective optimization. The optimization algorithm for simultaneous optimization computes and produces three-dimensional alignments in Pareto front at the end of the optimization run. The results show that the SFCL can reduce the volt-ampere… Show more

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Cited by 55 publications
(39 citation statements)
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“…Thus, the limitation performance is the multisided interaction between the fault current, temperature, current depended on resistance, variable resistance of HTS substrate and other specification in the external power system [22]. The Table 1 shows the characteristic table of SFCL which is used for simulation [23]. We can represent the resistive SFCL (Rsfcl) as a function of different parameters given in Eq.…”
Section: Modeling Of Resistive Sfclmentioning
confidence: 99%
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“…Thus, the limitation performance is the multisided interaction between the fault current, temperature, current depended on resistance, variable resistance of HTS substrate and other specification in the external power system [22]. The Table 1 shows the characteristic table of SFCL which is used for simulation [23]. We can represent the resistive SFCL (Rsfcl) as a function of different parameters given in Eq.…”
Section: Modeling Of Resistive Sfclmentioning
confidence: 99%
“…Normal conducting state at a temperature above the critical value. In flux state, the flux resistance depends on the HTS temperature (T) and the instantaneous value of current density (J) [23,24].…”
Section: Modeling Of Resistive Sfclmentioning
confidence: 99%
“…One of the comprehensive systems for many of power quality problems, such as current harmonics, reactive power, and source voltage distortions, is Unified Power Quality Conditioner (UPQC) [4]. It consists of two back to back connected series and shunt Voltage Source Inverters (VSIs) with a common dc link [5][6][7][8][9]. In all of the previous contributions of series and shunt inverters DC link capacitor is a major part of compensator.…”
Section: Introductionmentioning
confidence: 99%
“…Classification of different UPQC topologies has been presented by V. Khadkikar [7]. Several other control strategies have been described in different literatures [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][29][30]. Axente et al [8] proposed a sequence based compensation strategy to compensate both balanced and unbalanced sags.…”
mentioning
confidence: 99%
“…A digital signal processor based microcontroller is used for the implementation of the control algorithm. Heydari et al [12] described about the design of combination of UPQC and superconducting fault current limiter(SFCL) which is based on normalized simulated annealing algorithm. Use of SFCL reduces the cost of installation of UPQC by reducing volt-ampere rating of UPQC as it limits the fault current.…”
mentioning
confidence: 99%