A new method for designing digital cell libraries is presented where basic building blocks for logic and memory may be built from identical stacks of transistors in series, only, simplifying the design. Simulations in subthreshold operation is included, suggesting that the method could in principle be used for any synchronous finite state machine. A standard 4 transistor implementation and an 8-transistor version using our suggested approach, having equal total areas, are compared using statistical simulations in 65 nm CMOS, taking local variations into account. The average standard deviations of circuit delays for the traditional NAND implementation were then less than half (44 %), when compared to the new 8 transistor implementation. Anyway, for the same sizing, the traditional NAND2 had about twice the total active area, about 37 % higher static power consumption, 127 % higher active power consumption and about 51 % higher energy per operation, according to simulations. The static power consumption was also about 33 % higher for the traditional NAND, compared to the suggested approach based on combining a couple of 4-transistor "slices". Combining identical "'slices"' of transistors enabling in principle a range of combinatorial and memory building blocks could greatly simplify library cell design, or subsets of cell libraries.
A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and the pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency.
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