Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing

Vatanjou, Ali Asghar; Låte, Even; Ytterdal, Trond; Aunet, Snorre

doi:10.1016/j.micpro.2017.11.002

Cited by 3 publications

(6 citation statements)

References 9 publications

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“…It has been done to see the effect of 22 nm versus 28 nm FDSOI technology on ultra low voltage design problems. Energy per operation and leakage current obtained for all full adders in this study are much lower than [6] and [14]. The amount of energy per addition for [6] is more than 12X of that for the Xor based adder in this study.…”

Section: Discussionmentioning

confidence: 53%

“…Energy per operation and leakage current obtained for all full adders in this study are much lower than [6] and [14]. The amount of energy per addition for [6] is more than 12X of that for the Xor based adder in this study. Leakage is a key issue in ultra low voltage design.…”

Section: Discussionmentioning

confidence: 53%

“…Since all full adders have been designed with HVT devices with reverse back bias voltage, leakage current for the five full adders in this study is much lower than the amount showed in TABLE VIII. The leakage current of the 1-bit adder in [6] is more than 3X that of the Xor based adder in this study.…”

Section: Discussionmentioning

confidence: 62%

“…As listed in Tables II, III, IV and V, the leakage current of the full adder based on Nand is the largest and it is 1.11, 2.16, 2.03 and 3.62 times as much as that of the full adders based on Nand-Nor, Minority, standard and Xor, respectively. To see VIII shows the amount of energy per addition and the leakage current for [6] and [14] in 28 nm FDSOI technology; these parameters have been compared with the result of this study. It has been done to see the effect of 22 nm versus 28 nm FDSOI technology on ultra low voltage design problems.…”

Section: Discussionmentioning

confidence: 99%

“…In this technology, the efficiency of body biasing technique has been increased by controlling the channel. Body bias technique in FDSOI and CMOS technology has been used in many works to reduce supply voltage and hence circuit power consumption [5], [6], [7]. In this paper, an extended body bias technique has been used in a commercially available 22 nm FDSOI technology.…”

Section: Introductionmentioning

confidence: 99%

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Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology

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Aunet

2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Five ultra low voltage and low power full adders have been designed and analyzed with CMOS logic structure. To compare these adders, different metrics including worst case delay, average power, PDP, and PDP*Leakage have been investigated in the supply voltage varying from 140-160 mV. All the full adders have been designed and verified with Cadence Virtuoso design in a commercially available 22 nm FDSOI technology. An extended body bias voltages introduced in a 22 nm FDSOI technology have been used to balance Pull Up/Pull Down Networks and have a high functional yield. The test bench has been used to verify the functionality of full adders automatically in different conditions of temperature and supply voltage. The simulation results show that an Xor based adder is the best of all having the lowest delay, power, PDP, and PDP*Leakage in different conditions.

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Section: Discussionmentioning

confidence: 53%

Section: Discussionmentioning

confidence: 53%

Section: Discussionmentioning

confidence: 62%

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology

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Aunet

2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Self Cite

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Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders

Zadeh

Ytterdal

Aunet

2020

2020 IEEE Nordic Circuits and Systems Conference (NorCAS)

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Optical and electrical programmable computing energy use comparison

Cole

2021

Opt. Express

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Optical computing has been proposed as a replacement for electrical computing to reduce energy use of math intensive programmable applications like machine learning. Objective energy use comparison requires that data transfer is separated from computing and made constant, with only computing variable. Three operations compared in this manner are multiplication, addition and inner product. For each, it is found that energy use is dominated by data transfer, and that computing energy use is a small fraction of the total. Switching to optical from electrical programmable computing does not reduce energy use.

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Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing

Cited by 3 publications

References 9 publications

Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology

Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology

Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders

Optical and electrical programmable computing energy use comparison

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