An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

Abstract

A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and the pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency.

An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique

“…4 illustrates the behavioral simulation of the proposed LS circuit, demonstrating that its functionality can be configured to perform NAND and NOR logic operations with time borrowing effect. The analysis of the LS circuit can be broken down into four parts, namely (i) re-configurable logic in the To further reduce the current contention problem while reducing the power consumption of the LS circuit, we have adopted diode-connected transistors MP5 and MP6 in the PUN [13]. Similar to [29], the P-type transistors MP3 and MP4 regulate the strength of the PUN, allowing faster output transition while reducing its dynamic power consumption.…”