Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI

Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes

“…The D flip-flop (triggered in negative edge) is realized using TG based master-slave model as shown in Fig. 1 which is same in structure with positive edge triggered PowerPC 603 flip-flop [2][3][4]. In this paper clock gating technique restricts the clock signal to a clock network when it is not in use.…”