We report a new InP/GaAsSb double heterojunction bipolar transistor (DHBT) emitter fin architecture with a record f MAX = 1.2 THz, a simultaneous f T = 475 GHz, and BV CEO = 5.4 V. The resulting BV CEO × f MAX = 6.48 THz-V is unparalleled in semiconductor technology. Devices were realized with a 20-nm-thick compositionally and impurity graded GaAsSb-base and a 125-nm InP collector. The performance arises because the process allows: 1) a tunable base-emitter access distance down to 10 nm; 2) the use of thicker base contact metals; and 3) the minimization of parasitic capacitances and resistances via precise lateral wet etching of the base-collector (B/C) mesa. Perhaps more significantly, InP/GaAsSb DHBTs with f MAX ≥ 1 THz are demonstrated with emitter lengths as long as 9.4 μm and areas as high as 1.645 μm 2 . Such an area is >6× larger than previously reported terahertz (THz) DHBTs, representing a breakthrough in THz transistor scalability. This attractive performance level is achieved with a very low dissipated power density which makes InP/GaAsSb DHBTs well-suited for high-efficiency millimeter-and submillimeter-wave applications. Furthermore, we provide the first large-signal characterization of a THz transistor with 94 GHz load-pull measurements showing a peak power-added-efficiency (PAE) of 32.5% (40% collector efficiency) and a maximum saturated power of 6.67 mW/μm 2 or 1.17 mW/μm of emitter length in a common-emitter configuration. Devices operate stably under large-signal conditions, with voltages nearly twice higher than those for peak small-signal performance.
This paper reports a detailed approach towards optimization of on-wafer TRL calibration structures for submillimeter-wave characterization of a state-of-the-art InP technology, validated by thorough experimentation and electromagnetic (EM) simulation. The limitations of the existing RF test structures for high frequency measurements beyond 110 GHz are analyzed through EM simulation. Using an optimization procedure based on calibration of raw EM simulated data, onwafer TRL calibration structures were developed and fabricated in a subsequent run of this technology. Measurements could be achieved up to 500 GHz on the passive devices and up to 330 GHz on the InP DHBTs. The transistor measurements were validated by comparison with the HiCuM compact model simulation to 330 GHz for the InP DHBTs.
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