FIR lter is an essential part of digital signal processing that is extensively used in many areas such as wireless application and digital processing system. An e cient recursive lter is always required for realtime applications such as 5G network, smart robots and Internet of Things etc. The design of FIR lter is inherently stable and has a linear phase characteristic but its implementation often involves complexity and a large lter length to achieve speci c design requirements. In this paper, the complexity of FIR lter is reduced by eliminating the repeated subexpression in a canonic sign digit(CSD)number system based lter operation. A new grouping method has been proposed for the CSD number system-based lter coe cient to minimize the number of unpaired nonzero bits in the lter coe cient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11% as compared to other existing schemes. Further, an e cient FIR lter with hardware sharing architecture is designed and implemented to achieve a 14.65% reduction in average power consumption and the average operation speed is increased by 10.1% in comparison to the other existing lter structures.
Optimization of power, speed and hardware utilization are the major concerns in design objectives for modern digital signal processing (DSP) applications. In intermediate frequency (IF) processing unit of SDR receivers, a FIR filter is the main processing element. The redundant number system is extensively used to optimize the arithmetic operations in digital systems. This implementation can further be improved through an architectural transformation at circuit level. In this paper, the use of hybrid signed digit (HSD) number based filter coefficients is proposed for a FIR filter design. Based on the proposed HSD coefficient method in filter computation, a reduction of 16.06% in hardware resources is achieved in comparison to existing methods. In addition, a retiming architecture for an optimized FIR filter is proposed and compared with other existing approaches. The average power consumption is reduced by 13.42% and increases speed by 10.13% in comparison to other existing structures.
FIR filter is an essential part of digital signal processing that is extensively used in many areas such as wireless application and digital processing system. An efficient recursive filter is always required for real-time applications such as 5G network, smart robots and Internet of Things etc. The design of FIR filter is inherently stable and has a linear phase characteristic but its implementation often involves complexity and a large filter length to achieve specific design requirements. In this paper, the complexity of FIR filter is reduced by eliminating the repeated subexpression in a canonic sign digit(CSD)number system based filter operation. A new grouping method has been proposed for the CSD number system-based filter coefficient to minimize the number of unpaired nonzero bits in the filter coefficient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11% as compared to other existing schemes. Further, an efficient FIR filter with hardware sharing architecture is designed and implemented to achieve a 14.65% reduction in average power consumption and the average operation speed is increased by 10.1% in comparison to the other existing filter structures.
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