HSD based Computationally Efficient FIR Filter with Retiming Architecture for SDR Application

Abstract

Optimization of power, speed and hardware utilization are the major concerns in design objectives for modern digital signal processing (DSP) applications. In intermediate frequency (IF) processing unit of SDR receivers, a FIR filter is the main processing element. The redundant number system is extensively used to optimize the arithmetic operations in digital systems. This implementation can further be improved through an architectural transformation at circuit level. In this paper, the use of hybrid signed digit (HSD) number based filter coefficients is proposed for a FIR filter design. Based on the proposed HSD coefficient method in filter computation, a reduction of 16.06% in hardware resources is achieved in comparison to existing methods. In addition, a retiming architecture for an optimized FIR filter is proposed and compared with other existing approaches. The average power consumption is reduced by 13.42% and increases speed by 10.13% in comparison to other existing structures.