An Efficient FIR Filter Based on Hardware Sharing Architecture Using CSD Coefficient Grouping for Wireless Application

Abstract

FIR lter is an essential part of digital signal processing that is extensively used in many areas such as wireless application and digital processing system. An e cient recursive lter is always required for realtime applications such as 5G network, smart robots and Internet of Things etc. The design of FIR lter is inherently stable and has a linear phase characteristic but its implementation often involves complexity and a large lter length to achieve speci c design requirements. In this paper, the complexity of FIR lter is reduced by eliminating the repeated subexpression in a canonic sign digit(CSD)number system based lter operation. A new grouping method has been proposed for the CSD number system-based lter coe cient to minimize the number of unpaired nonzero bits in the lter coe cient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11% as compared to other existing schemes. Further, an e cient FIR lter with hardware sharing architecture is designed and implemented to achieve a 14.65% reduction in average power consumption and the average operation speed is increased by 10.1% in comparison to the other existing lter structures.