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Embedded reconfigurable architectures are currently attracting increasing attention in the wireless communications industry due to the escalating number of wireless standards in today's market. Application specific instruction-set processors (ASIPs) present a reconfigurable solution that offers a compromise between programmability and low power consumption. In this article, the design and implementation of an embedded synchronization and acquisition ASIP for OFDM based systems is proposed. The engine architecture is presented and the programming model is explained in details. The proposed engine is scalable and it can be configured to support a multitude of synchronization algorithms and OFDM standards. While applicable to many OFDM systems, the proposed architecture was successfully verified on long term evolution (LTE Rel. 8) and WiMAX 802.16e systems. A partial list of synchronization and acquisition algorithms are tested on the engine for the two standards, and the results highlight the capabilities of the engine. The processor has been synthesized with 0.18μm standard cell CMOS library. It is estimated to occupy 1.1 mm 2 and the projected power consumption is 7.9mW at 120 MHz, which meets the speed requirements of the tested standards. More results are included within the article.

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In this paper, A novel architecture of an Application Specific Instruction Processor (ASIP) for scalable DFT/IDFT DCT/IDCT 1D (N-point) and 2D (N × M point) engine is proposed. An in place configurable radix 2/3/4 butterfly, makes possible the implementation of two radix N/M is varied in the form of 2 x × 3 y . Therefore the engine can support different communication and signal processing applications. A new address generator scheme is proposed which achieves conflict-free memory access. This scheme is based on partitioning the memory to 4 dual-port memory banks with a continuous address generator to accommodate high-speed requirements. Using same reduction techniques, the twiddle factors memory size is reduced to 28%. By taking advantage of programmability, the engine provides more configurability and flexibility in switching between modes in run-time. Moreover it can be easily adapt to new applications. The DFT/DCT engine requires only 1280 clock cycles for a 1024-point DFT-1D and runs at 120 MHz with SQNR 75.2 dB.

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