Embedded reconfigurable synchronization &amp; acquisition ASIP for a multi-standard OFDM receiver

Said, Mahmoud A; Nasr, Omar A.; Shalash, Ahmed F.

doi:10.1186/1687-3963-2012-2

Cited by 4 publications

(15 citation statements)

References 17 publications

(32 reference statements)

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“…For example, adding another complex multiplier in the TTA based solution is simply to add another SFU instance for complex multiplication and make connections to the bus network. However, adding a new FU in a conventional ASIP [Said and Shalash 2012] design or hardware accelerator [Harju and Nurmi 2005] requires careful thought and may require considerable changes in the existing interconnection of FUs, RFs, and control logic. So the simplest way to scale the architectures in Said and Shalash [2012] and Harju and Nurmi [2005] is to use another instance of the proposed design, as also suggested in Said and Shalash [2012].…”

Section: Scalabilitymentioning

confidence: 99%

“…However, since all the units are somehow connected to each other, it should widen the range of applications that will perform better. The data path presented in Said and Shalash [2012] also has FUs that are general in nature and could be used in various baseband processing tasks. However, in Harju and Nurmi [2005], the carrier synchronization is performed by a hardware accelerator attached to a RISC core.…”

Section: Flexibilitymentioning

confidence: 99%

“…In this section, the proposed architecture has been evaluated with various aspects of the processing architectures presented in Harju and Nurmi [2005] and Said and Shalash [2012]. The simulation parameters used in the experiment are shown in Table I.…”

Section: Evaluation and Comparisonmentioning

confidence: 99%

“…In Said and Shalash [2012], the proposed engine is programmed in its native assembly code. Writing a code in assembly is a tedious job since the programmer has to have knowledge of the underlying hardware details.…”

Section: Programmingmentioning

confidence: 99%

“…Different reconfigurable solutions for radio baseband processing tasks have been proposed in Said and Shalash [2012] and Harju and Nurmi [2005]. The architecture is under consideration is a unique concept named TTA (Transport Triggered Architecture) and is considered as a potential candidate for SDR Platforms.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Transport triggered architecture to perform carrier synchronization for LTE

Anjum

Ali

Pitkänen

et al. 2014

ACM Trans. Embed. Comput. Syst.

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In this article implementation of carrier frequency offset estimate for 20MHz LTE baseband processing is discussed. LTE (Long Term Evolution) is a wireless communication standard that makes use of some innovative techniques to gain very high data rates (>100Mbps). This goal for such a high throughput also imposes design challenges for the industry and academia such as in the case of handheld mobile devices where the power budget is very limited. Implicitly high throughput means we need more computation power and more energy. On the other hand industry is also struggling for a flexible hardware solution, or software defined a radio (SDR), to amortize the huge cost of required hardware changes as the wireless standards have kept evolving. Design innovations are now needed to confront those challenges of low power and flexible design without changing the hardware. The implementation is made on Transport Triggered Architecture (TTA), which is a unique concept in computer architecture design, based on the single instruction, "MOVE". The power consumption of the architecture when synthesized on 180nm technology at 180MHz and 1.8V is 18.39mW. The total area occupied excluding memory is 0.6mm 2 . The proposed TTA solution has been compared with, a more ASIC (application specific integrated circuits), like ASIP (application specific instruction processor) solution and a coprocessor accelerator-based solution. The proposed solution is more flexible: easily programmable due to high level language support, easily scalable, and still efficient in energy consumption needed to complete the CFO (carrier frequency offset) estimation task. Because of these attractive characteristics, TTA is also a potential candidate for SDR platforms.

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Section: Scalabilitymentioning

confidence: 99%

Section: Flexibilitymentioning

confidence: 99%

Section: Evaluation and Comparisonmentioning

confidence: 99%

Section: Programmingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Transport triggered architecture to perform carrier synchronization for LTE

Anjum

Ali

Pitkänen

et al. 2014

ACM Trans. Embed. Comput. Syst.

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Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor

All¹,

Hassan²,

Hamdy³

et al. 2015

IET Circuits, Devices & Systems

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The two implementation choices for the baseband part of wireless radios are the application-specific platforms (e.g. application-specific integrated circuits (ASICs)) and the programmable processors (e.g. digital signal processors (DSPs)). An application-specific instruction-set processor (ASIP) is a customised processor that bridges the gap between the two platforms. In this work, a novel implementation of the signal processing part of an orthogonal frequency division multiplexing (OFDM) baseband processor using three ASIPs is presented. The ASIPs provide novel architectures for the symbol chain, including fast Fourier transform, channel estimation subsystem and synchronisation subsystem. This design provides a close to DSPs level of flexibility, making it suitable for supporting all the modes of a large number of OFDM standards. In the meantime, the system maintains a performance level comparable to ASICs. This is demonstrated by providing post-layout results for 0.13 μm Taiwan semiconductor manufacturing company complementary metal-oxide semiconductor technology.

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