This paper presents an in-depth review of the critical front end stages of the fabricated integrated circuit (IC) assurance workflow used for recovering the design stack-up of a fabricated IC. In this work, a Serial Peripheral Interface (SPI) embedded on a 130 nm static random access memory (SRAM) chip is targeted for recovering the full design stack-up. This process leverages state-of-the-art techniques for high precision material processing and image acquisition to optimize and ensure the highest accuracy in the feature extraction stage. To this end, we present metrics that can be leveraged for optimizing the front end stages of the assurance workflow. Novel imaging figures of merit (FOM) for optimizing image acquisition parameters have been developed and are presented. The Image Quality Factor (IQF) FOM was established to quantify overall image quality as it pertains to feature extraction and the Quality and Efficiency Rating (QER) FOM was demonstrated to optimize imaging parameter selection, balancing image quality and image acquisition time.
Trusted design and verification presents new challenges for the case of using Intellectual Property (IP) in mixed signal systems. A Digitally Controlled Oscillator (DCO) subcomponent of a Phase-Locked Loop (PLL) is utilized as an example through which the presented verification principles may be applied to PLL tests on the Texas Instruments Analog System Lab Kit Pro (TI ASLK Pro). A VHDL model has also been developed, incorporating Assertion-Based Verification (ABV) as a means for trusted verification of the design.
Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.
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