IC Decomposition and Imaging Metrics to Optimize Design File Recovery for Verification and Validation

Abstract

This paper presents an in-depth review of the critical front end stages of the fabricated integrated circuit (IC) assurance workflow used for recovering the design stack-up of a fabricated IC. In this work, a Serial Peripheral Interface (SPI) embedded on a 130 nm static random access memory (SRAM) chip is targeted for recovering the full design stack-up. This process leverages state-of-the-art techniques for high precision material processing and image acquisition to optimize and ensure the highest accuracy in the feature extraction stage. To this end, we present metrics that can be leveraged for optimizing the front end stages of the assurance workflow. Novel imaging figures of merit (FOM) for optimizing image acquisition parameters have been developed and are presented. The Image Quality Factor (IQF) FOM was established to quantify overall image quality as it pertains to feature extraction and the Quality and Efficiency Rating (QER) FOM was demonstrated to optimize imaging parameter selection, balancing image quality and image acquisition time.

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

“…The layout of the FEOL and MOL is displayed in the cross-sectional scanning transmission electron micrograph in Figure 2. Leveraging previous sample preparation workflow developments, each layer of this device required either front side or back side delayering workflows in preparation for imaging [4]. In the front-side delayering workflow, the BEOL layers needed to be removed to approach the FEOL and MOL layers.…”

“…In our previous efforts, we demonstrated the full design extractions of a 130 nm node region of interest (ROI) [4] and a 45 nm node ROI [5]. The focus of this study was on the sample preparation, imaging, and design extraction of the Front-End-of-Line (FEOL) and Middle-of-Line (MOL) layers of a 14 nm node FinFET device.…”