A Decomposition Workflow for Integrated Circuit Verification and Validation

Kimura, Adam; Scholl, Jon; Schaffranek, James; Sutter, Matthew; Elliott, Andrew; Strizich, Mike; Via, G. D.

doi:10.1007/s41635-019-00086-6

Cited by 31 publications

(13 citation statements)

References 6 publications

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“…With layout-level and gate-level obfuscation applied, it is possible for the SME to incorrectly identify a logic gate. The consequence of incorrect logic gate assignment was demonstrated in the example in Figure 2 and objectively assessed in a RE case study where the authors reported that the time frame required for error resolution was larger than the time frame required for imaging the IC [19].…”

Section: B Random Interactionsmentioning

confidence: 99%

“…There are several works that perform RE on a particular IC, typically a smart card, as a case study for reporting on the challenges and resources cost incurred during the work [6], [19], [58]- [61]. The modules in the RE workflow shown in Figure 1 mostly acts as a placeholder.…”

Section: B Impact Of Ad-hoc Processes On Hardware Assurancementioning

confidence: 99%

“…The expansion of the workflow associated with the annotation module is shown in Figure 17. With a reliable annotation module built, the gatelevel netlist can be obtained using the standard cell library, including using available design data, manual template matching [19], [45], [64], [65] or other automated approaches [46]. There are several approaches that are available for hardware assurance at the netlist extraction module.…”

Section: Performance Analysismentioning

confidence: 99%

“…Similarly, there are several image segmentation evaluation metrics, such as the Intersectionover-Union (IoU) and Structural Similarity Index Measure (SSIM), that are capable of evaluating segmentation based on shapes but are inherently incapable of incorporating electrical connectivity information into account. They lead to short-circuits or modification of the intended functionality resulting in significant inflation of RE process time frame to account for manual error resolution [19]. As demonstrated in the examples, a deeper understanding of the domain and its inherent challenges needs to be acquired before datadriven approaches can be fully integrated into the hardware assurance problem.…”

Section: Introductionmentioning

confidence: 99%

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REFICS: Assimilating Data-Driven Paradigms Into Reverse Engineering and Hardware Assurance on Integrated Circuits

Wilson¹,

Zhu

et al. 2021

IEEE Access

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Comprehensive hardware assurance approaches guaranteeing trust on Integrated Circuits (ICs) typically require the verification of the IC design layout and functionality through destructive Reverse Engineering (RE). It is a resource intensive process that will benefit greatly from the extensive integration of data-driven paradigms, especially in the imaging and image analysis phase. Although obvious, this uptake of data-driven approaches into RE-assisted hardware assurance is lagging due to the lack of massive amounts of high-quality labelled data. In this paper, a large-scale synthetic Scanning Electron Microscopy (SEM) dataset, REFICS, is introduced to address this issue. The dataset, the first open-source dataset in the RE community, consists of 800,000 SEM images over two node technologies, 32nm and 90nm, and four cardinal layers of the IC, namely, doping, polysilicon, contact and metal layers. Furthermore, a framework, based on uncertainty and risk, is introduced to compare the efficacy and benefits of existing RE workflows utilizing ad-hoc steps in its execution. These developments are critical in developing RE-assisted hardware assurance into a scalable, automated and fault-tolerant approach. Finally, the work is concluded with the performance analysis of existing machine learning and deep learning approaches for image analysis in RE and hardware assurance.

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Section: B Random Interactionsmentioning

confidence: 99%

Section: B Impact Of Ad-hoc Processes On Hardware Assurancementioning

confidence: 99%

Section: Performance Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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REFICS: Assimilating Data-Driven Paradigms Into Reverse Engineering and Hardware Assurance on Integrated Circuits

Wilson¹,

Zhu

et al. 2021

IEEE Access

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“…The focus of this study was on the sample preparation, imaging, and design extraction of the Front-End-of-Line (FEOL) and Middle-of-Line (MOL) layers of a 14 nm node FinFET device. Covering the first three of the five steps in the cooperative V&V workflow [6], this collective work is not only applicable for the V&V community, but failure analysis and other adjacent communities. The demonstration of sample preparation techniques, imaging, and design extraction of the FEOL/MOL in a 14 nm FinFET device are herein presented for the first time in peer reviewed literature.…”

Section: Introductionmentioning

confidence: 99%

Preparation, Imaging, and Design Extraction of the Front-End-of-Line and Middle-of-Line in a 14 nm Node FinFET Device

Waite¹,

Patel²,

Kelley³

et al. 2021

Preprint

Self Cite

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This paper presents the first design reconstruction on the Front-End-of-Line and Middle-of-Line layers of a 14 nm node FinFET design. To accomplish this, a large region of interest within a custom designed 14 nm node ASIC device was delayered, imaged, and analyzed to reconstruct the GDSII design file and verify a 100% match to the golden GDSII design. This work leveraged previous developments in each stage of the front half of the cooperative Verification and Validation (V&V) workflow combined with new techniques and processes developed for processing 3D architecture FET devices. We have demonstrated the critical first step to performing a full V&V workflow on an advanced technology node device, starting from the fabricated silicon device to the design extraction. The process development knowledge gained while reaching this milestone will further accelerate future advancements toward providing trusted advanced technology node devices in a timely manner. <br>

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