The IEEE P1149.4 Mixed-Signal Test Bus Working Group is on the cusp of delivering a document that will finally standardize the architecture for, and the method of access to, the analog portion of mixed-signal circuits f o r test and diagnostic applications. This Standard will have the same profound effect on the design arid test community that IEEE 1149.1 [ I ] had almost 8 years ago.P1149.4 gives the test infrastructure the capability to measure discrete impedances external to devices supporting the Standard using a 6-wire bus. This bus uses 4 of the same signals used today to support 1149. I compliant devices and subsystems. This paper will detail the basic architecture; give some design-specific information and data learned through the Standard's development process: relate results from several test devices; and provide a basic example of usage.
IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist. * Yu Li is currently with the ; Ming Shao is currently with Punch Powertrain, ming.shao@punchpowertrain.com; Hailong Jiao is currently also with the Shenzhen Graduate School of Peking University, jiaohl@pkusz.edu.cn. 2018 23rd IEEE European Test Symposium (ETS) !
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