International audienceIn this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using Through-Silicon-Vias (TSVs). Indeed, TSV-based 3D integration allows to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D-NoC. Intrinsically, 3D topologies have better performances, but yield and active area (and thus the cost) are function of the number of TSVs; therefore, the designs tend to use only a subset of available TSVs between two dies. The definition of blockage free and low implementation cost distributed deterministic routing on this kind of topology is thus of theoretical and practical interests. We formally prove that independently of the shape and dimensions of the planar topologies and of the number and placement of the TSVs, the proposed routing algorithm using two virtual channels in the plane is deadlock and livelock free. We also experimentally show that the performance of this algorithm is still acceptable when the number of vertical connections decreases

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International audienceNetworks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment

ISBN 978-1-4673-2234-8International audienceIn this paper, we detail the design and implementation of a router for vertically-partially-connected 3D-NoCs based on stacked 2D-meshes. This router implements the necessary hardware to support a recently introduced routing algorithm called "Elevator-First", which targets topologies with irregularly placed vertical connections in a deadlock free manner, using only two virtual channels in the plane. The micro-architectural design shows that the proposed router requires few additional hardware. Our studies about the practicality of the algorithm and its router implementation demonstrate that it has low overhead compared to a router for fully connected 3D-NoCs. Using ST Microelectronics 65nm CMOS technology Elevator-First router with 7 ports has a total area of 0.07mm², an Operating frequency of over 3GHz and a power consumption of around 3mW

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ISBN :8-1-4419-7617-8The shrinking of processing technology in the deep submicron domain aggravates the imbalance between gate delays and wire delays. While a Network-on-Chip systematically tackles this physical issue by differentiating between local and global interconnects, 3D-Integration by folding the die into multiple layers and using short vertical links instead of long horizontal interconnects, leads to a considerable reduction in the length and the number of long global wires. This chapter elaborates on the strategic exploitation of these two key technologies, where the use of the third dimension in the design of the integrated networks provides a major improvement in the network performance. It makes a case for using asynchronous circuits to implement 3D-NoCs. We claim that asynchronous logic allows benefiting from serialized vertical link leading to the definition of innovative architectures which can address some critical issues of 3D integrated circuits using Through-Silicon-Vias. This allows complying with the cost-efficiency trade-off of the 3D-Integration paradigm

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