Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Sheibanyrad, Abbas; Greiner, Alain; Miro-Panades, Ivan

doi:10.1109/mdt.2008.167

Cited by 52 publications

(19 citation statements)

References 10 publications

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“…The work in [16] has presented a multisynchronous and fully asynchronous NoCs for GALS architecture. The asynchronous data communication between NoC switches is synchronized by using dual-clock FIFO buffers as a multisynchronous domain.…”

Section: Related Workmentioning

confidence: 99%

“…The bisynchronous FIFO buffer is then clocked by the clock signal from the data transmitter side for FIFO-write operation mode, and by clock signal from the data receiver side for FIFO-read operation mode. Since metastability issue (synchronization failure) probably occurs by using the multisynchronous approach, the work in [16] proposes also the fully asynchronous approach by providing synchronous interfaces to each local subsystem.…”

Section: Related Workmentioning

confidence: 99%

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Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems

Samman

Philipp

Glesner

2011

2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE)

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A concept for reconfigurable communication infrastructure for networked control systems is presented in this paper. The communication infrastructure consists of two communication protocols, i.e. wireless communication and wired communication protocols. The concept is dedicated for a hard real-time distributed parameter control system, where each local control module is implemented as a platform with multiple/interconnected reconfigurable and programmable devices such as Field-programmable Gate Arrays (FPGAs) and microcontrollers. Adaptive networked multiprocessing algorithms can be further mapped onto the platform for specific real-time control applications. Data exchanges between multiple control units on a hardware platform are controlled by multicast-enabled switches that are also implemented on the FPGA devices. Data exchanges between platforms in a more complex system are controlled by a wireless standard communication protocol. The exchanged data can be sensor signals, actuating signals and system parameters. A bit-level parallel handshaking interface (PHI) adapter is introduced to handle the inter-switch data communication between the FPGA devices.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems

Samman

Philipp

Glesner

2011

2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE)

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“…Although having many potential advantages such as high throughput communication, high scalability and versatility, as well as good power management efficiency, the NoC paradigm must deal with the difficulty of distributing a synchronous clock signals through the entire large area chip [3], [4]. The Globally Asynchronous, Locally Asynchronous (GALS) approach attempts to address this issue by partition the chip into many multiple functional islands [5]. Since each island is clocked by a different clock signal, safely transmitting data between different clock domains becomes a big challenge for designing NoCs based on GALS, especially reconfigurable NoCs.…”

Section: Introductionmentioning

confidence: 99%

A novel asynchronous first-in-first-out adapting to multi-synchronous network-on-chips

Nguyen

Tran

2014

2014 International Conference on Advanced Technologies for Communications (ATC 2014)

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The integration of a variety of IP cores into a single chip to meet the high demand of new applications leads to many challenges in timing issues, especially the interface between different clock domains. Globally Asynchronous, Locally Synchronous (GALS) approach addresses these challenges by dividing a chip into several independent subsystems working with different clock signals. In multi-synchronous Network-on-Chip (NoC) based on GALS architecture, the network routers run with different frequencies, so the problem is how to transfer data safely and efficiently between them. In order to build a synchronization unit to tackle this problem, in this paper, we propose a novel efficient asynchronous First-In-First-Out architecture targeting to multi-synchronous NoCs. Token ring structure, register-based memory, and modified Asynchronous AssertionSynchronous De-assertion techniques are applied to improve the performance of the proposed asynchronous FIFO. After simulating and verifying the design, we have implemented our asynchronous FIFO architecture with CMOS 180nm technology from AMS. Implementation results are analyzed and compared with previous works to show the strong points of our design.

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“…An asynchronous design is a good candidate for NoC paradigm. It enables the GALS systems to operate in multi clock frequencies [5], and moves the synchronization issue only in the point of interfacing the synchronous IP with the NoC infrastructure [6].…”

Section: Introductionmentioning

confidence: 99%

A High Throughput Low Power FIFO Used for GALS NoC Buffers

Fattah

Manian

Rahimi

et al. 2010

2010 IEEE Computer Society Annual Symposium on VLSI

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In Networks-on-chip, increasing the depth of routers' buffers even by a few stages can have a significant effect on average latency and saturation threshold of the network. However, the price to pay could be high in terms of power and silicon area. In this paper, we propose a low power, high throughput asynchronous FIFO suitable for buffers of GALS NoC routers. We consistently compare the performance with regards to power, area and throughput of our FIFO with some different FIFO structures, by exploring their design trade-offs with various number of stages and for different data lengths. These structures are simulated in 90nm CMOS technology with accurate spice simulations, where results show a low power consumption and latency, with a higher throughput. Finally, a back-annotated HDL model of a 4x4 mesh network, wherein a fully asynchronous router is implemented, shows better average latency, saturation threshold and power tradeoffs, using the proposed FIFO.

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Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Cited by 52 publications

References 10 publications

Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems

Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems

A novel asynchronous first-in-first-out adapting to multi-synchronous network-on-chips

A High Throughput Low Power FIFO Used for GALS NoC Buffers

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