No abstract

No abstract

Abstract-This paper presents the first synthesizable network-on-chip (NoC) based on a mesh topology, which supports adaptive and deadlock-free tree-based multicast routing without virtual channels. The deadlock-free routing algorithms for unicast and multicast packets are the same. Therefore, the routing function gate-level implementation is very efficient. Multicast packets are injected to the network by sending multiple packet headers beforehand. The packet headers contain destination addresses to set up multicast trees connecting a source with multiple destination nodes. An additional locally uniform identification (ID) field is packetized together with flits belonging to the same packet. Therefore, flits of different unicast or multicast packets can be interleaved in the same queue because of the local ID-tags, which are updated and mapped dynamically to support bandwidth scalability of interconnection links. Deadlocks in tree-based multicast routing are handled using a flit-by-flit round arbitration and a fair hold-release tagging mechanism. The effectiveness of the novel mechanism has been experimented under multiple multicast conflicts scenarios, where the experimental results show that all traffic is accepted in-order and lossless in their destination nodes even if adaptive routing functions are used and the sizes of the multicast messages are very long.Index Terms-Network-on-chip (NoC), tree-based multicast routing, synchronous parallel pipeline, wormhole packet switching.

No abstract

No abstract

Routing is one of the most crucial key factors which will decide over the success of NoC architecture based systems or their failure. This paper uses well known principles from parallel computer architecture to develop a deadlock free highly adaptive routing algorithm for a 2D-Mesh based Network-on-Chip (NoC) architecture including oversized IP cores. The paper consists of a short introduction into related routing theories and then gives a detailed description of the developed routing scheme. The last part is dedicated to a new floorplanning method, which allows to generate high density layouts suitable for the presented routing algorithm.

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

Abstract-The design of digital electronic systems for industrial applications can benefit in many ways from the prototyping capabilities of field-programmable gate array (FPGA) platforms. This paper presents three evolutionary releases of an FPGA-based remote laboratory and discusses the didactical and technical motivations behind each release, aiming to reduce the overhead of setting up and operate a laboratory environment where designers and students can use FPGA prototyping to validate their designs. To achieve that, a number of abstraction layers were introduced, allowing configuration and data processing in remote FPGA platforms, as well as integrating such platforms within a simulation environment. The proposed approach supported a number of projects where groups of designers and students could specify, refine, and prototype electronic systems using a pool of remotely available FPGA platforms.Index Terms-Design automation, field-programmable gate arrays (FPGAs), integrated circuit design, remote laboratories.