A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Panades, Ivan Miro; Greiner, Alain; Sheibanyrad, Abbas

doi:10.1109/nanonet.2006.346219

Cited by 62 publications

(50 citation statements)

References 20 publications

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“…Our third major source of inspiration was previous work on the design of general-purpose many-core architectures using the SoCLib virtual prototyping library [15] and the DSPIN NoC [16]. Our work extends this NoC to provide good support to off-line real-time scheduling.…”

Section: Related Workmentioning

confidence: 99%

“…As pictured in Fig. 1, the tiled many-cores of SoCLib are composed of a rectangular set of tiles connected through a state-of-the-art 2D synchronous mesh network-on-chip (NoC) called DSPIN [16]. The NoC is formed of a command NoC and a response NoC which are fully separated.…”

Section: A Tiled Many-cores In Soclibmentioning

confidence: 99%

“…The DSPIN network-on-chip [16] is a classical 2D mesh NoC. It uses wormhole packet switching and a static routing 1 Consecutive writes inside a single cache line are buffered.…”

Section: Modifications Of the Nocmentioning

confidence: 99%

“…Enforcing fixed packet transmission orders requires the use 2 X-first routing for the command network and Y-first for the response network. 3 Unless a two-level virtual channel mechanism is used, as described in [16].…”

Section: Modifications Of the Nocmentioning

confidence: 99%

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Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-We start from a general-purpose many-core architecture designed for average-case performance and ease of use. In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain. We modify this architecture and extend the code generation flow to allow the construction of efficient hard real-time systems starting from dependent task specifications. We rely on a static (off-line) real-time scheduling paradigm welladapted to embedded control and signal processing applications with regular control structure.We modify the architecture (and in particular the on-chip network) to allow the implementation of static schedules with very high (clock cycle) temporal precision. On the software side, we define application mapping rules ensuring that the timing precision provided by the hardware is not lost. These mapping rules include requirements on the allocation of data variables to specific RAM banks and on the use of locks to ensure the absence of contentions during access to shared resources. Applications complying with these rules can be written manually or automatically obtained using a new mapping tool that takes all the allocation and scheduling decisions. Compilation of the resulting C code is still done using the (unmodified) gcc compiler chain. The resulting platform provides good performance, and at the same provides very high timing precision, as shown by two case studies (an embedded controller and an implementation of the FFT).We conclude our paper with a presentation of some ongoing work on the subject: A case study (an implementation of the H.264 decoder) meant to test the limitations of our method.

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Section: Related Workmentioning

confidence: 99%

Section: A Tiled Many-cores In Soclibmentioning

confidence: 99%

“…The DSPIN network-on-chip [16] is a classical 2D mesh NoC. It uses wormhole packet switching and a static routing 1 Consecutive writes inside a single cache line are buffered.…”

Section: Modifications Of the Nocmentioning

confidence: 99%

Section: Modifications Of the Nocmentioning

confidence: 99%

See 2 more Smart Citations

Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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“…The original DSPIN [9], [10] was designed by the LIP6 laboratory and was physically implemented by ST Microelectronics, to support MP2SoC architecture). In this paper, DSPIN is the selftestable&cleanable, reconfigurable version.…”

Section: A Noc-based Shared Memory Mp2socmentioning

confidence: 99%

Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure

Zhang¹,

Refauvelet²,

Greiner³

et al. 2011

29th VLSI Test Symposium

Self Cite

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Abstract-In this paper, we present a software approach for localization of faulty components in a 2D-mesh Network-onChip, targeting fault tolerance in a shared memory MP2SoC architecture. We use a pre-existing and distributed hardware infrastructure supporting self-test and de-activation of the faulty components (routers and communication channels), that are transformed into "black hole". We detail the software method used to localize these "black holes", and centralize the information in a single point, where a modified global routing function can be defined. This embedded software makes an extensive use of a distributed fault-tolerant configuration firmware assisted by a Distributed Cooperative Configuration Infrastructure (DCCI), that is also presented. Finally, "black hole" detection and localization coverage is evaluated.

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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

Sethi

Hussin

Hamid

2018

IEEJ Transactions Elec Engng

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Network-on-chip (NoC) is a communication framework for multiple cores connected together in a system-on-chip (SoC). Different NoC architectures have provided quality of service (QoS) parameters of best effort (BE) and guaranteed throughput (GT). GT services are provided by having a dedicated connection using circuit switching or connection-oriented mechanism of packet switching. GT traffic is usually preferred for real-time traffic such as video processing and multimedia applications. BE services are provided using packet switching. Cache updates is an example of BE noncritical traffic. In this paper, we implement a novel biologically inspired fault-tolerant algorithm that provides both GT and BE QoS. In order to provide fault tolerance, the router architectures is also updated. The bio-inspired, fault-tolerant techniques are a novel way to provide fault tolerance in NoC. Faults in the NoC arise as the size of the devices are shrinking on the NoC, which include the router, links, and processing elements (PEs), to accommodate the complex communication requirements of applications. The proposed NoC's fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain's robust fault-tolerant mechanisms. From the experimental results, the throughput and bandwidth utilization are dropped by 3.55 and 4.87%, respectively, during the recovery from faults. The interflit arrival time and packet network latency are increased by only 7.03 and 22.60%, respectively, during the recovery from faults. The algorithm also performs as efficiently as the traditional fault-tolerant techniques.

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A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Cited by 62 publications

References 20 publications

Reconciling performance and predictability on a many-core through off-line mapping

Reconciling performance and predictability on a many-core through off-line mapping

Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure

Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

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