Los autores discuten la tendencia hacia el consumo de productos artesanales en los mercados de las economías desarrolladas y se preguntan si el valor artesanal radica en la “marca” de los productos artesanales o en el “saper fare” (saber hacer) como valor intrínseco de la artesanía tradicional. A partir de algunos ejemplos de la Toscana, se analiza el valor agregado de la innovación en las cadenas de valor globales (que conjugan actividades dispares como la marca, el diseño y la fabricación en distintas regiones), en contraste con el valor elemental de la práctica artesanal tradicional, localizada e histórica. En esta comparación se discute la base filosófica del “saber hacer”; cómo la artesanía impregna un producto con identidad intrínseca o “aura”; y el papel crucial del “genius loci” (espíritu del lugar) en la comprensión del producto artesanal y su proceso. Se argumenta que los procesos habilitados para GVC (cadenas de valor globales) han relegado a artesanos toscanos altamente calificados a ser proveedores de mano de obra de los diseñadores de lujo globales y de los gerentes de marca. Por último, los autores sostienen que “la artesanía de avanzada” –que comprende métodos ágiles y adaptables que permiten las técnicas de producción digital– se puede combinar con el “saper fare” italiano para colocar a los artesanos expertos en el centro del proceso estratégico, promoviendo que artesanos y diseñadores compartan información como co-creadores y diseñadores. Por lo tanto, este concepto de “artesanía de avanzada” promete mejorar la participación de la Toscana en la creación de valor de la región y de Italia
Despite its widespread use in consumer devices and enterprise storage systems, NAND flash faces a growing number of challenges. While technology advances have helped to increase the storage density and reduce costs, they have also led to reduced endurance and larger block variations, which cannot be compensated solely by stronger ECC or read-retry schemes but have to be addressed holistically. Our goal is to enable low-cost NAND flash in enterprise storage for cost efficiency. We present novel flash-management approaches that reduce write amplification, achieve better wear leveling, and enhance endurance without sacrificing performance. We introduce block calibration, a technique to determine optimal read-threshold voltage levels that minimize error rates, and novel garbage-collection as well as data-placement schemes that alleviate the effects of block health variability and show how these techniques complement one another and thereby achieve enterprise storage requirements. By combining the proposed schemes, we improve endurance by up to 15× compared to the baseline endurance of NAND flash without using a stronger ECC scheme. The flash-management algorithms presented herein were designed and implemented in simulators, hardware test platforms, and eventually in the flash controllers of production enterprise all-flash arrays. Their effectiveness has been validated across thousands of customer deployments since 2015.
In the discretization of the 3-D partial differential equations of many physics problems, it is found that the resultant system of linear equations can be represented by a block tridiagonal matrix. Depending on the substructure of the blocks, one can devise many algorithms for the solution of these systems. For plasma physics problems of interest to the authors, several interesting matrix problems arise that should be useful in other applications as well. In one case, where the blocks are dense, it was found that by using a multitasked cyclic reduction procedure, it was possible to reach gigaflop rates on a Cray-2 for the direct solve of these large linear systems. The recently built code PAMS (parallelized matrix solver) embodies this technique and uses fast vendor-supplied routines and obtains this good performance. Manipulations within the blocks are done by these highly optimized linear algebra subroutines that exploit vectorization as well as overlap of the functional units within each CPU. In unitasking mode, speeds well above 340 Mflops have been measured. The cyclic reduction method multitasks quite well with overlap factors in the range of three to four. In multitasking mode, average speeds of 1.1 gigaflops have been measured for the entire PAMS algorithm. In addition to the presentation of the PAMS algorithm, it is shown how related systems having banded blocks may be treated efficiently by multitasked cyclic reduction in the Cray-2 multiprocessor environment. The PAMS method is intended for multiprocessors and would not be a method of choice on a uniprocessor. Furthermore, this method’s advantage was found to be critically dependent on the hardware, software, and charging algorithm installed on any given multiprocessor system.
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