Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory

Παπανδρεου, Νικολαοσ; Pozidis, Haralampos; Parnell, Thomas; Ioannou, Nikolas; Pletka, Roman; Tomić, Saša; Breen, Patrick; Tressler, Gary; Fry, Aaron; Fisher, Timothy S.

doi:10.1109/irps.2019.8720454

Cited by 30 publications

(7 citation statements)

References 9 publications

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“…The BER is expressed by dividing the model into two parts: one without parity overhead and one with it. The initial RBER in Figure 8 was taken from the reference paper [22], and the error rate value indicated by each model in Figure 8 can be regarded as the average error rate value of each cluster. Furthermore, the black line near the error rate of 10 −15 represents the industry standard error rate for a typical SSD [23].…”

Section: Apply Differentiated Data Protection Policymentioning

confidence: 99%

“…1. For RBER, the value measured in 3D TLC NAND flash memory [22] is used for calculating our analytical model. 2.…”

Section: Apply Differentiated Data Protection Policymentioning

confidence: 99%

“…Figure 9b shows the comparison of BER when ECC provided by default is applied to RBER. In addition, the RBER of Figure 9a was measured based on 9K P/E cycles of 3D TLC NAND flash memory [22]. Retention time, which is the x-axis of the graph, is a parameter indicating when a certain period has elapsed after data was saved, and was quantitatively evaluated by dividing it into four sections at two-week intervals from week 0 to week 6. stripe is 2, the Differentiated Protection model considering parity overhead in Figure 8 is shown by referring to the result of 50% increase in WAF.…”

Section: Hot/cold-aware Data Placement Structure Appliedmentioning

confidence: 99%

See 2 more Smart Citations

Differentiated Protection and Hot/Cold-Aware Data Placement Policies through k-Means Clustering Analysis for 3D-NAND SSDs

Son¹,

Kim²

2022

Electronics

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3D-NAND flash memory provides high capacity per unit area by stacking 2D-NAND cells having a planar structure. However, because of the nature of the lamination process, the frequency of error occurrence varies depending on each layer or physical cell location. This phenomenon becomes more pronounced as the number of flash memory write/erase (Program/Erasure) operations increases. Error correction code (ECC) is used for error correction in the majority of flash-based storage devices, such as SSDs (Solid State Drive). As this method provides a constant level of data protection for all-flash memory pages, there is a limitation in 3D-NAND flash memory, where the error rate varies depending on physical location. Consequently, in this paper, pages and layers with varying error rates are classified into clusters using the k-means machine-learning algorithm, and each cluster is assigned a different level of data protection strength. We classify pages and layers based on the number of error occurrences measured at the end of the endurance test, and for areas vulnerable to errors, it is shown as an example of providing differentiated data protection strength by adding parity data to the stripe. Furthermore, areas vulnerable to retention errors are identified based on retention error rates, and bit error rates are significantly reduced through our hot/cold-aware data placement policy. We show that the proposed differential data protection and hot/cold-aware data placement policies improve the reliability and lifespan of 3D-NAND flash memory compared with the existing ECC- or RAID-type data protection scheme.

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Section: Apply Differentiated Data Protection Policymentioning

confidence: 99%

“…1. For RBER, the value measured in 3D TLC NAND flash memory [22] is used for calculating our analytical model. 2.…”

Section: Apply Differentiated Data Protection Policymentioning

confidence: 99%

Section: Hot/cold-aware Data Placement Structure Appliedmentioning

confidence: 99%

See 1 more Smart Citation

Differentiated Protection and Hot/Cold-Aware Data Placement Policies through k-Means Clustering Analysis for 3D-NAND SSDs

Son¹,

Kim²

2022

Electronics

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“…The BER of 3D NAND is generally lower than that of 2D NAND. Particularly, the relationship between the number of P/E cycles and increase of BER is the same for both [40,[42][43][44]. In this paper, we use BER as the reliability criterion for flash memory storage.…”

Section: Reliability Of Flash Memorymentioning

confidence: 99%

Building Reliable Massive Capacity SSDs through a Flash Aware RAID-Like Protection

Kim

Park

2020

Applied Sciences

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The demand for mass storage devices has become an inevitable consequence of the explosive increase in data volume. The three-dimensional (3D) vertical NAND (V-NAND) and quad-level cell (QLC) technologies rapidly accelerate the capacity increase of flash memory based storage system, such as SSDs (Solid State Drives). Massive capacity SSDs adopt dozens or hundreds of flash memory chips in order to implement large capacity storage. However, employing such a large number of flash chips increases the error rate in SSDs. A RAID-like technique inside an SSD has been used in a variety of commercial products, along with various studies, in order to protect user data. With the advent of new types of massive storage devices, studies on the design of RAID-like protection techniques for such huge capacity SSDs are important and essential. In this paper, we propose a massive SSD-Aware Parity Logging (mSAPL) scheme that protects against n-failures at the same time in a stripe, where n is protection strength that is specified by the user. The proposed technique allows for us to choose the strength of protection for user data. We implemented mSAPL on a trace-based simulator and evaluated it with real-world I/O workload traces. In addition, we quantitatively analyze the error rates of a flash based SSD for different RAID-like configurations with analytic models. We show that mSAPL outperforms the state-of-the-art RAID-like technique in the performance and reliability.

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“…Many previous studies have conducted experiments to characterize the performance and reliability features of planar and 3D NAND flash and make meticulous analyses [23,26,32,33]. It is a common practice to understand the flash retention errors through high-temperature baking processes [2,3,7,32,33].…”

Section: Introductionmentioning

confidence: 99%

How the common retention acceleration method of 3D NAND flash memory goes wrong?

Kuo

2021

Proceedings of the 13th ACM Workshop on Hot Topics in Storage and File Systems

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The reliability of solid-state drives (SSDs) has become increasingly important as SSDs are now widely applied in data centers. Retention error is a major source of impact on the reliability of SSDs. Even though the common practice in understanding the retention errors of an SSD is done by high-temperature baking processes, their characterization accuracy is not yet rigidly reviewed. In this paper, we first present how the common retention acceleration method goes wrong. Through a one-year study of 3D flash error behaviors, we found that the retention errors through baking with high temperatures have very different characteristics from the real long-retention errors. These differences come from the inherent structure and the materials of 3D NAND flash. Several findings regarding the retention errors characterized through baking are presented, followed by the analysis of the error behaviors. Finally, the retention errors of one year on 3D flash memory are provided with real data.

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Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory

Cited by 30 publications

References 9 publications

Differentiated Protection and Hot/Cold-Aware Data Placement Policies through k-Means Clustering Analysis for 3D-NAND SSDs

Differentiated Protection and Hot/Cold-Aware Data Placement Policies through k-Means Clustering Analysis for 3D-NAND SSDs

Building Reliable Massive Capacity SSDs through a Flash Aware RAID-Like Protection

How the common retention acceleration method of 3D NAND flash memory goes wrong?

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