Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash

Παπανδρεου, Νικολαοσ; Pozidis, Haralampos; Ioannou, Nikolas; Parnell, Thomas; Pletka, Roman; Stanisavljević, Miloš; Stoica, Radu; Tomić, Saša; Breen, Patrick; Tressler, Gary; Fry, Aaron; Fisher, Timothy S.; Walls, Andrew

doi:10.1109/irps45951.2020.9129620

Cited by 13 publications

(1 citation statement)

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“…To further reduce the number of learned segments, LeaFTL performs optimizations to improve its learning efficiency of address mappings by exploiting the flash block allocation in SSD controllers, as shown in Figure 7. Flash pages are usually buffered in the SSD controller and written to flash chips at a flash block granularity, for utilizing the internal bandwidth and avoiding the open-block problem [6,22,37,48]. This allows LeaFTL to learn more space-efficient index segments (i.e., index segments can cover more LPA-PPA mappings) by reordering the flash pages with their LPAs in the data buffer.…”

Section: Improve the Learning Efficiencymentioning

confidence: 99%

LeaFTL: A Learning-Based Flash Translation Layer for Solid-State Drives

Sun¹,

Li²,

Sun³

et al. 2023

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems,

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In modern solid-state drives (SSDs), the indexing of flash pages is a critical component in their storage controllers. It not only affects the data access performance, but also determines the efficiency of the precious in-device DRAM resource. A variety of address mapping schemes and optimizations have been proposed. However, most of them were developed with human-driven heuristics.In this paper, we present a learning-based flash translation layer (FTL), named LeaFTL, which learns the address mapping to tolerate dynamic data access patterns via linear regression at runtime. By grouping a large set of mapping entries into a learned segment, it significantly reduces the memory footprint of the address mapping table, which further benefits the data caching in SSD controllers. LeaFTL also employs various optimization techniques, including out-of-band metadata verification to tolerate mispredictions, optimized flash allocation, and dynamic compaction of learned index segments. We implement LeaFTL with both a validated SSD simulator and a real open-channel SSD board. Our evaluation with various storage workloads demonstrates that LeaFTL saves the memory consumption of the mapping table by 2.9× and improves the storage performance by 1.4× on average, in comparison with state-of-the-art FTL schemes.

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Section: Improve the Learning Efficiencymentioning

confidence: 99%