Post cycling data retention reliability model of NROM devices is presented. The degradation rate of the threshold voltage of cycled cells is shown to be a multiplication of three functions: 1) bit density; 2) endurance; and 3) storage time and temperature. The functions are fitted to experimental results of products of three technology nodes. The retention loss is interpreted in terms of thermally activated lateral migration of trapped holes in the ONO layer. The holes' migration quenches the electrons' field over the channel of the device, degrading its threshold voltage. The migration process is presented as a dispersive transport process. Saturation of the retention loss is demonstrated at threshold voltage levels well above the neutral state of the device. From the retention loss function we derive a time-to-failure formula and an expression for the thermal acceleration factor of NROM products useful for determining stress conditions for accelerated reliability tests.
A spectroscopy method is proposed and implemented for Si3Ni4 layer using the NROM® cell and the gate-induced-drain-leakage measurement. The proposed method allows probing of both electron and hole traps in the entire band gap with almost no fitting parameters. The energy levels of occupied charge traps are extracted following a thermionic emission model. It is found that the peak energy distribution of the electron traps is located ∼2.2eV below the nitride conduction band with a full width at half maximum (FWHM) of 0.16eV, while the peak energy distribution of the hole traps is located ∼1.5eV above the nitride valence band with a FWHM of 0.64eV. Based on these results, the retention loss of the NROM cell is successfully predicted over a wide range of temperatures and time scales.
The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming algorithm (3MB/s write speed), no single bit failures and window sensing with moving reference as an error detection and correction scheme.
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