This paper describes a monolithically integrated ω z -gyroscope fabricated in a surface-micromaching technology. As functional structure, a 10 µm thick Silicon-Germanium layer is processed above a standard high voltage 0.35 µm CMOS-ASIC. Drive and Sense of the in plane double wing gyroscope is fully capacitively. Measurement of movement is also done fully capacitively in continuous-time baseband sensing. For characterization, the gyroscope chip is mounted on a breadboard with auxiliary circuits. A noise floor of 0.01 °/s/sqrt(Hz) for operation at 3 mBar is achieved.
The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectrónica de Sevilla and Universidad de Sevilla (IMSE-USE) have started a long term collaboration with the Spanish Instituto Nacional de Técnica Aeroespacial (INTA) to extend its experience on mixed-signal design to the field of ASICs for space applications. The assessment of a commercial (austriamicrosystems) 0.35µm CMOS technology is a first step towards the development of a mixed-signal design methodology, including the development of an RHBD digital library suitable for use in space conditions.
Future MEMS devices require an increase in performance and a reduction in size of the sensor units as compared to current stateof-the-art devices. One way to achieve both goals is monolithic integration of MEMS with the driving, controlling, and signal processing electronics on the same substrate. This improves the performance of the MEMS due to the reduction of the parasitics arising from the MEMS-IC interconnections, allows for smaller packages, and leads to a lower packaging and instrumentation cost [1,2]. There are currently three approaches to achieve this monolithic integration of MEMS and embedded electronics [3]: processing the MEMS device first and integrated circuits last and typically next to each other [4]; mixing the fabrication of both [5]; and processing the integrated circuit first and the MEMS device last and typically on top of the circuitry.This last option is, in the authors' view, the most promising approach for monolithic integration as it allows the use of conventional CMOS processes and fairly independent optimization of the CMOS and MEMS processes. In addition, a new generation of circuitry can replace the older one without affecting the MEMS process. Moreover, post-processing provides the most compact form of putting MEMS and CMOS together as the CMOS circuitry can potentially be situated underneath the MEMS structures. However, post-processing limits the thermal budget for MEMS processing. MEMS processing at low temperatures can of course be done with materials such as resist sacrificial layers and metal structural layers, e.g., Al. The disadvantages are however that Allayers are not very stiff, intrinsic quality factors are low, stress gradients are high and that they suffer from severe reliability problems such as creep. Poly-SiGe provides the desired mechanical and electrical properties for MEMS applications at significantly lower temperatures [6,7] compared to poly-Si (>800°C). Poly-SiGe is therefore an attractive material for processing MEMS above CMOS. LPCVD poly-SiGe has already been used to make a thin (~2.5µm thick) integrated resonator on top of a 3µm CMOS process with 1 metal layer [2].In this work integrated poly-SiGe gyroscopes are made above 8" standard CMOS wafers using 3 extra mask steps (Fig. 4.7.1 and Fig. 4.7.2). The CMOS technology used is a 0.35µm process with 5 metal layers (top 4 layers are Al interconnects) and standard passivation. After the deposition and patterning of an etchstop layer, a thick undoped sacrificial Si-oxide layer is deposited. This Si-oxide layer is planarized by the use of CMP and 4×28µm 2 contacts to the top metal layer are etched through the sacrificial layer, the etchstop layer, and the CMOS passivation stack. The 10µm thick poly-SiGe structural layer, that also forms the contact with the top metal, is deposited by using an advanced multi-layer technology combining CVD without plasma and plasmaenhanced chemical vapor deposition (PECVD). With this technique, high-quality films are obtained at low temperature (≤450°C) with very high depositio...
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