A 10 μm thick poly-SiGe gyroscope processed above 0.35 μm CMOS

Abstract

This paper describes a monolithically integrated ω z -gyroscope fabricated in a surface-micromaching technology. As functional structure, a 10 µm thick Silicon-Germanium layer is processed above a standard high voltage 0.35 µm CMOS-ASIC. Drive and Sense of the in plane double wing gyroscope is fully capacitively. Measurement of movement is also done fully capacitively in continuous-time baseband sensing. For characterization, the gyroscope chip is mounted on a breadboard with auxiliary circuits. A noise floor of 0.01 °/s/sqrt(Hz) for operation at 3 mBar is achieved.

Introduction

“…In the past, imec already proved the potential of poly-SiGe for MEMS-above-CMOS integration by presenting, for example, an integrated poly-SiGe micromirror array [2] and an integrated gyroscope [3], both of them fabricated on top of aluminum-based CMOS (from an external foundry). However, the aggressive interconnect scaling, essential to the continuation of Moore's law, has led to the replacement of the traditional aluminum metallization by copper metallization, due to its lower resistivity and improved reliability [4].…”

“…The first CMOS-integrated poly-SiGe device was a resonator presented by UC Berkley in [22]. In [3], imec presented CMOS-integrated gyroscopes processed on top of 0.35 µm CMOS wafers with five levels of aluminum metal interconnects. In [2], CMOS-integrated 10 cm 2 11-megapixel SiGe-based micromirror arrays were presented.…”

CMOS-integrated sige MEMS: Application to micro-mirrors

“…However, because of the high deposition rate, PECVD normally requires higher deposition temperatures [12] in order to obtain crystalline layers in-situ, as desired for good MEMS structural layers. To integrate the first functional poly-SiGe-based gyroscope above 0.35 µm industrial CMOS (Figure 3, [13]), a multilayer process that combines PECVD and CVD was used. With this trick, high-quality films can be obtained at low temperature (≤ 450ºC) with very high deposition rates (~100nm/min) [14].…”

“…A low resistivity of 1.45 mΩcm, a tensile residual stress of 35 MPa and a very low strain gradient of 3.6×10 -6 μm -1 were achieved for 10 μm thick films using a top Si-rich stress compensation layer. Figure 3: Optical microscope picture of free standing SiGe gyroscope processed above CMOS [13] For the micro-mirrors discussed in this paper, another poly-SiGe deposition process was developed. A PECVDbased hydrogenated micro-crystalline SiGe (μcSiGe:H) deposition process [13] at 400ºC was chosen in order to obtain small SiGe grains (50 -100 nm).…”

“…Figure 3: Optical microscope picture of free standing SiGe gyroscope processed above CMOS [13] For the micro-mirrors discussed in this paper, another poly-SiGe deposition process was developed. A PECVDbased hydrogenated micro-crystalline SiGe (μcSiGe:H) deposition process [13] at 400ºC was chosen in order to obtain small SiGe grains (50 -100 nm). The small grains ensure uniform and reproducible mechanical properties of the 350nm wide hinges of the micro-mirrors.…”