Introduction:We report measurements of the DC characteristics of sub-l00nm nMOSFETs that employ low leakage. ultra-thin gate oxides only 1 -2nm thick to achieve high current drive capability and transconductance. We demonstrate that ZDsctr=: 1.8mAIp.m can be achieved with a 60nm gate at 1.5V using a 1.3-1.4nm gate oxide with a gate leakage current less than 20r~AIp.m~. Furthermore, we find that ZDscrr deteriorates for gate oxides thicker or thinner than this.Fabrication: We have explored a gate stack consisting of l00nm of TEOS hard mask over 80nm of doped W.5, on 1 00nm of in-situ phosphorus-doped poly-crystalline silicon on gate oxides ranging in thickness from 1 -2nm thick on a ptype epitaxial silicon. Prior to the oxide growth, the substrates were stripped by immersion into a 15: 1 H 2 0: HF solution for only 5 seconds (to minimize surface roughness and pitting) and then subjected to a vapor phase clean in 10 Torr
A transition to a low carbon energy system is needed to respond to global challenge of climate change mitigation. Aquifer Thermal Energy Storage (ATES) is a technology with worldwide potential to provide sustainable space heating and cooling by (seasonal) storage and recovery of heat in the subsurface. However, adoption of ATES varies strongly across Europe, because of both technical as well as organizational barriers, e.g. differences in climatic and subsurface conditions and legislation respectively. After identification of all these barriers in a Climate-KIC research project, six ATES pilot systems have been installed in five different EU-countries aiming to show how such barriers can be overcome. This paper presents the results of the barrier analysis and of the pilot plants. The barriers are categorized in general barriers, and barriers for mature and immature markets. Two pilots show how ATES can be successfully used to redevelop contaminated sites by combining ATES with soil remediation. Two other pilots show the added value of ATES because its storage capacity enables the utilization of solar heat in combination with solar power production.
As the drive towards the production of 100 nm CMOS devices pick up speed, the practical aspect of transistor shallow junction formation, including a large menu of process integration issues, must now be solved in a short order. The most direct path to 50 nm junction depths is through the sub-keV boron implantation and rapid thermal annealing.The material aspects of the process integration centers on: (1) CMOS devices for shallow, highly-activated and abrupt junctions (involving the choice of ion species [B, BF, B10H14, BSi2, etc.], substrate materials [ Cz, Epi, SOI], anneal conditions [ramp rate, soak time, ambient gas], etc.) and (2) Defect-dopant interactions during annealing (including surface reactions of high concentration species [B, F], diffusion and carrier trapping by background and co-implanted species [C, 0, F, etc.].Process data for atomic and electrical activity profiles as well as defect and interface structures will be presented to illustrate progress towards understanding these complex process interactions. A particular focus will be the effects of anneal ambient and rapid temperature rise times approaching the “pike” anneal ideal.
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