In agreement with the ITRS roadmap, there have been several publications supporting the reduction in critical dimensions and the introduction of new materials to semiconductor processing (1,2,3). This paper highlights the observations and solutions to some of the critical material and process interactions encountered during the integration of the back end of line interconnect.
A method of integrating high performance and low-cost Cu ultra low-k (ULK) SiOC(k=2.0) hybrid interconnects with SiOC(k=2.65) hard mask structure has been developed. The method combines Cu/ULK interconnects with the self-formed MnO x barrier layer that was shown to have lower resistance and higher reliability than Cu alloys. Moreover, dual-damascene (DD) interconnects with MnO x barrier layer showed excellent stress-induced voiding performance and significantly longer electromigration lifetime and required no additional pore-sealing process. It is concluded that this self-formed barrier process is the most feasible technology for 32nm-node Cu/ULK interconnects.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.