Thermally robust cu interconnects with Cu-Ag alloy for sub 45nm node

Isobayashi, A.; Enomoto, Y.; Yamada, H.; Takahashi, S.; Kadomura, S.

doi:10.1109/iedm.2004.1419342

Cited by 12 publications

(12 citation statements)

References 5 publications

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“…Fig. 13 shows copper resistivity as a function of wire width for aspect ratios 1.4 and 1.6, and also contains experimental results for comparison purposes [47]- [51]; 20 -cm resistivity was subsequently used to calculate the sheet resistance for 6.4 nm wide interconnects. Similarly, contact resistance was extrapolated from experimental data on 100 nm and larger via diameters and resulted in 18.5 for each metal contact as shown in Fig.…”

Section: A Parasitic Extraction and Postlayout Issuesmentioning

confidence: 99%

“…Similarly, contact resistance was extrapolated from experimental data on 100 nm and larger via diameters and resulted in 18.5 for each metal contact as shown in Fig. 14 [48]- [51]. The estimations on contact resistance and wire resistivity likely contain errors since these parameters are extracted either from a technology that supports 100 nm wire features or extrapolated from a simplified scattering model that does not take account crucial scattering mechanisms such as interface (wire surface) and grain boundary scattering [52].…”

Section: A Parasitic Extraction and Postlayout Issuesmentioning

confidence: 99%

See 1 more Smart Citation

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal

Naresh

Yuan

et al. 2007

IEEE Trans. Nanotechnology

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This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit OFF currents under 1 pA while producing highest ON currents. DC characteristics of the optimum and -channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2-and 3-input NAND, NOR, and XOR gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 m 2 .Index Terms-Low-power very large scale integration (VLSI), metal-gate transistors, nanowire transistors, vertical silicon transistors.

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Section: A Parasitic Extraction and Postlayout Issuesmentioning

confidence: 99%

Section: A Parasitic Extraction and Postlayout Issuesmentioning

confidence: 99%

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal

Naresh

Yuan

et al. 2007

IEEE Trans. Nanotechnology

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“…Another method to improve the electromigration lifetime is to dope the Cu with impurities such as Al [135,136], Ag [137], or Mn [138][139][140]. The dopants are typically introduced into the Cu seed layer (Figure 8.21H-K).…”

Section: Electromigrationmentioning

confidence: 99%

“…The main problem with this approach is that the impurities increase the resistivity of Cu. However, increases in resistivity of 3-10% are observed for most of these impurities [135,137]. However, increases in resistivity of 3-10% are observed for most of these impurities [135,137].…”

Section: Electromigrationmentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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“…The electromigration resistance of Cu can be improved through doping with elements such as Ag, Sn, and Al [1][2][3]. Since the current density increases with shrinking feature size, Cu lines become more and more prone to electromigration-induced failure.…”

Section: Introductionmentioning

confidence: 99%

Al Diffusion in Polycrystalline Cu

et al. 2008

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The diffusion of aluminum (Al) from a source sandwiched between polycrystalline copper (Cu) thin films was investigated as a function of time and temperature through secondary ion mass spectroscopy (SIMS) and continuum simulations. Extracted diffusion coefficients for the bulk were in line with literature values. In order to simulate the experimentally derived diffusion profiles at temperatures where bulk diffusion is not the dominant diffusion mechanism (room temperature to 350 °C), it was necessary to explicitly include the re-distribution of Al as a result of Cu grain growth during anneal. Aluminum has the tendency to segregate to the Cu/liner and Cu/etch stop (ES) interface. The tendency of Al to segregate to the liner is ten times stronger for ruthenium (Ru) than for tantalum (Ta). In 100 nm wide dual damascene structures lined with Ru, this segregation behavior was responsible for the Al depletion in bulk Cu and for the Al depletion at the Cu/ES interface.

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Thermally robust cu interconnects with Cu-Ag alloy for sub 45nm node

Cited by 12 publications

References 5 publications

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Process Technology for Copper Interconnects

Al Diffusion in Polycrystalline Cu

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