Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as process and electrical parameters. In this paper, pattern (i.e. density, width and space) dependent interconnect thickness and width variations are studied based on a well-designed test chip in a 90 nm technology. The parasitic resistance and capacitance variations due to the process variations are investigated, and process-variation-aware extraction techniques are proposed. In the test chip, electrical and physical measurements show strong metal thickness and width variations mainly due to chemical mechanical polishing (CMP) in nanometer technologies. The loop inductance dependence of return patterns is also validated in the test chip. The proposed new characterization methods extract interconnect RC variations as a function of metal density, width and space. Simulation results show excellent agreement between on-wafer measurements and extractions of various RC structures, including a set of metal loaded/unloaded ring oscillators in a complex wiring environment.
Abstract-Dummy fills are being extensively used to enhance CMP planarity. However presence of these fills can have a significant impact on the values of interconnect capacitances. Accurate capacitance extraction accounting for these dummies is CPU intensive and cumbersome. For one, there are typically hundreds to thousands of dummy fills in a small layout region, which stress the general purpose capacitance extractor. Second, since these dummy fills are not introduced by the designers, it is of no interest for them to see the capacitances to dummy fills in the extraction reports; they are interested in equivalent capacitances associated with signal power and ground nets. Hence extracting equivalent capacitances across nets of interest in the presence of large number of dummy fills is an important and challenging problem. We present a novel extension to the widely popular MonteCarlo capacitance extraction technique. Our extension handles the dummy fills efficiently. We demonstrate the accuracy and scalability of our approach by two methods (i) classical and golden technique of finding equivalent interconnect capacitances by eliminating dummy fills through the network reduction method and (ii) comparing extracted capacitances with measurement data from a test chip.
Noise glitches can cause timing degradation in switching nodes or incorrect transitions in steady-state or "quiet" nodes. These incorrect transitions can propagate through the circuit, and can create functional errors or failures. This paper presents both a method and a practical implementation technique for accurately and efficiently characterizing and modeling the propagation of noise glitches through a cell within an integrated circuit. A characterization methodology is developed to generate Noise Immunity Criteria (NIC) and Noise Propagation Tables (NPT) for a given cell library. The resulting look-up tables are appended to any standard gate-level library to be utilized by Static Timing and Noise Analysis (STNA) tools.
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