Simple gate charge (Qg) measurement technique for on-wafer statistical monitoring and modeling of power semiconductor devices

Krishnamurthy, V.; Gyure, A.; Francis, P.

doi:10.1109/icmts.2012.6190627

Cited by 4 publications

(3 citation statements)

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“…However, due to extremely low parasitic capacitance value in GaN-on-Si HEMTs, a gate charge experimental measurement setup is difficult to design because of parasitic components in polarization circuit. A theoretical method has been proposed [10]: C-V measurement results can be used to determine gate-charge values by using the fundamental equation 1.…”

Section: Resultsmentioning

confidence: 99%

GaN HEMT devices: Experimental results on normally-on, normally-off and cascode configuration

Sorrentino

Melito

Patti

et al. 2013

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society

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Power electronics systems play key function in power management and motion control: power consumption and volume reduction are strongly required in new applications oriented to protect environment. Moreover, a switching frequency increase is demanded for microwave and power switching applications, thus reducing passive component and converter volume: however, increasing the switching frequency directly increases switching losses. Also, switching applications are very demanding, because semiconductor switches are required to withstand high voltage in reverse condition and handle large current in forward operation mode. New material and new devices are studied to satisfy such requirements, like SiC and GaN devices. In this work, several 600-V class GaN-on-Si HEMT prototypes are presented. These devices have been designed and developed for power switching converter applications. In order to offer a complete scenario of GaN-on-Si HEMT technology, normally-on, normally-off, and cascodeconnected devices have been characterized. Achieved experimental results of static and pulsed measurements are then shown. I INTRODUCTIONMicroelectronics today is dominated by silicon. Silicon (Si) power transistors performances have been dramatically improved thanks to technological improvements, but they have almost reached their theoretical limit. In order to overcome the silicon limits, new structures are designed to improve the device performance, such as MOSFET superjunction [1]. However, also these devices are limited in terms of performances respect to the higher performance required (energy saving, cost, size, etc). Hence, new materials have been studied like silicon carbide (SiC) and gallium nitride (GaN) to achieve further advances in power device performance [2]. Thanks to SiC and GaN intrinsic superior physical properties, silicon has reached the end of the road for power electronic devices. Gallium nitride high bandgap energy, high saturation velocity, and high electrical strength are only some of the main reasons for GaN success. Gallium nitride semiconductor devices are then emerging nowadays as attractive candidates in high power applications for carrying large currents and supporting high voltages, while providing very low on-resistance, low device capacitances and fast switching times [3]. GaN bandgap energy, E g ≈ 3.4 eV, is more than three times higher than that of Si (E g = 1.1 eV). The very large energy bandgap, i.e. the energy required to ionize atoms and create free electrons, is a fundamental property of GaN, making it extremely attractive for high-power and hightemperature applications; GaN energy bandgap is so large that the material is transparent. Moreover, high charge carrier mobility µ and high saturation velocity are attractive for high current and high frequency operation in a semiconductor device. Since the probability of intrinsic carrier generation and many other properties depend exponentially on the bandgap energy, a large bandgap is the key factor for high temperature operation and chemical inertne...

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Section: Resultsmentioning

confidence: 99%

GaN HEMT devices: Experimental results on normally-on, normally-off and cascode configuration

Sorrentino

Melito

Patti

et al. 2013

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society

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“…The simulated gate charge waveforms at V DS = 800 V and I DS = 10 A for the CON-MOS (30.3 nC) and the RG-MOS (34.9 nC) are provided in figure 7(b). For the fabricated devices, Q GD is extracted from the C-V method (figure 7(c)) rather than the conventional time-domain method to prevent introducing a load resistance or an inductance, which may bring in test-circuit parasitics and need large array teststructures [25]. Q GD is only enhanced by 1.04× for the RG-MOS (38.1 pF) compared with the CON-MOS (36.5 pF).…”

Section: Functional Mechanism Of Rg-mos On High-frequency Figures Of ...mentioning

confidence: 99%

Simultaneous improvement of high-frequency and Baliga figures of merit of 1.7 kV 4H-SiC MOSFET with retrograded JFET doping

Wang,

Hua,

Zheng

et al. 2024

J. Phys. D: Appl. Phys.

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The 1.7-kV 4H-SiC MOSFET which features optimized retrograded-profile ion implantation in the JFET regions (RG-MOS) is proposed and fabricated on the 4-inch wafers. The measured results quantify the benefits of the RG-MOS structure: simultaneous improvement in high-frequency figures of merit (HF-FOM) (Ron×CGD) by 1.5×, HF-FOM (Ron×QGD) by 1.5× and Baliga figure of merit (BFOM = 4BV2/Ron,sp) by 1.6× compared with the conventional MOSFET (CON-MOS). Unlike other reported complicated structures which need high-precise fabricating process, the proposed RG-MOS structure is compatible with the prior planar 4H-SiC MOSFET process, and is favorable for large-scale production.

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“…7.19a [25]. A load resistance R L ≫ R DS(on) is connected between the drain and the DC power supply, so that when transistor is on, most of the voltage drops across R L and the voltage at the MOSFET drain drops to near zero.…”

Section: Switching Performance R Ds(on) × Q Gmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Simple gate charge (Qg) measurement technique for on-wafer statistical monitoring and modeling of power semiconductor devices

Cited by 4 publications

References 0 publications

GaN HEMT devices: Experimental results on normally-on, normally-off and cascode configuration

GaN HEMT devices: Experimental results on normally-on, normally-off and cascode configuration

Simultaneous improvement of high-frequency and Baliga figures of merit of 1.7 kV 4H-SiC MOSFET with retrograded JFET doping

High-Voltage and Power Transistors

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