Presented in this paper is a realization of Multi-Layer Substrate with 30μm signal pattern width and 100μm square via holes on a 100 mm square ceramic substrate. To obtain this fine signal pattern width, a thin film technique, “GSP” process, has been applied on a thick film dielectric layer. For the 100μm square via holes through the thick film dielectric, a new thick film technique, “DD” process, has been developed utilizing a photolithographic technique. This paper describes the processes and the results obtained by the method.
This paper introduces the Polylmide-Ceramic substrate for NEC SX Supercomputers. In case of high performance system such as supercomputers and top end machines in general purpose computer, sophisticated packaging technologies are essential to achieve fastest operations as well as to use highestspeed, highly integrated LSIs.Wiring substrate which mounts and interconnects LSIs is the key to back up LSI's higher logical-operations.The high speed interconnection wirings and high density LSI mounting are requested for substrate.The Polyimide-Ceramic substrate had been developed to meet these demands and have many features of high density thin film wiring, high power supply, high thermal conductivity and huge number of I/Os, in addition to high speed wiring.25μm wide 75μm center-to-center spacing, two signal layers, 6ns/m signal transmissions, 2.5W/cm2 high power density, 2177 I/Os on a 100mm square substrate have been achieved by using this super substrate technology.The packaging hierarchy, the first level packaging of TAB LSI, the second level of multi-chip packaging by using Polyimide-Ceramic substrate and liquid cooling module, and the third level of board assemblies are introduced.
A fine-pitch ( less than 100 micro-meter pads pitch ) aluminum pad flip chip assembly technology for use with the built-up Printed Wiring Boards (PWB) has been developed and named “Lead-Less-Chip Assembly (LLC Assembly)” technology. Our newly developed technology consists of three points: Forming gold-ball-bumps on the aluminum pads of the bare LSI chip by a wire ball bonding method. Solder-coating on the copper pads of the built-up PWB using Micro Punching technology or the Super-Juffit technology. Flux-less solder bonding the bare chip onto the PWB with a nitrogen atmosphere.A reliability evaluation performed on a single chip and multi chip modules assembled using this LLC Assembly technology with test chips and real C-MOS devices showed a high level of endurance. We have applied this technology to Multichip modules (MCMs) for Note Personal Computers and portable terminals.
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