We propose that lateral heterostructures of single-atomic-layer graphene and hexagonal boron-carbon-nitrogen (hBCN) domains, can represent a powerful platform for the fabrication and the technological exploration of real two-dimensional field-effect transistors. Indeed, hBCN domains have an energy bandgap between 1 and 5 eV, and are lattice-matched with graphene; therefore they can be used in the channel of a FET to effectively inhibit charge transport when the transistor needs to be switched off. We show through ab initio and atomistic simulations that a FET with a graphene-hBCN-graphene heterostructure in the channel can exceed the requirements of the International Technology Roadmap for Semiconductors for logic transistors at the 10 and 7 nm technology nodes. Considering the main figures of merit for digital electronics, a FET with gate length of 7 nm at a supply voltage of 0.6 V exhibits I(on)/I(off) ratio larger than 10(4), intrinsic delay time of about 0.1 ps, and a power-delay-product close to 0.1 nJ/m. More complex graphene-hBCN heterostructures can allow the realization of different multifunctional devices, translating on a truly two-dimensional structure some of the device principles proposed during the first wave of nanoelectronics based on III-V heterostructures, as for example the resonant tunneling FET.

In this work, we present a performance analysis of Field Effect Transistors based on recently fabricated 100% hydrogenated graphene (the so-called graphane) and theoretically predicted semi-hydrogenated graphene (i.e. graphone).The approach is based on accurate calculations of the energy bands by means of GW approximation, subsequently fitted with a three-nearest neighbor (3NN) sp 3 tight-binding Hamiltonian, and finally used to compute ballistic transport in transistors based on functionalized graphene.Due to the large energy gap, the proposed devices have many of the advantages provided by one-dimensional graphene nanoribbon FETs, such as large Ion and Ion/I off ratios, reduced band-to-band tunneling, without the corresponding disadvantages in terms of prohibitive lithography and patterning requirements for circuit integration.

http://www.gianlucafiori.org/articles/betti_APL2011.pd

http://www.gianlucafiori.org/articles/betti_TED.pd

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