‘Zeppelin’: An SoC for multichip architectures

Beck, Noah; White, Sean; Paraschou, Milam; Naffziger, Samuel

doi:10.1109/isscc.2018.8310173

Cited by 67 publications

(25 citation statements)

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“…Interf. [149] Chip-to-Chip Ultra Path [150], [151] IFIS [33], [152]- [154] PCIe [155] CXL [156], [157] Cache Coh. (CCIX) [158] Gen-Z [159] OpenCAPI [160], [161] ?…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

“…The Infinity Fabric InterSocket (IFIS) [33], [152]- [154] of AMD ® implements package-to-package (i.e., socket-tosocket) communication to enable two-way multi-core processing. A typical IFIS interconnect has 16 transmit-receive differential data lanes, thereby providing bidirectional connectivity with data rates up to 37.93 GBs.…”

Section: B: Infinity Fabric Intersocket (Ifis)mentioning

confidence: 99%

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Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

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“…Interf. [149] Chip-to-Chip Ultra Path [150], [151] IFIS [33], [152]- [154] PCIe [155] CXL [156], [157] Cache Coh. (CCIX) [158] Gen-Z [159] OpenCAPI [160], [161] ?…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

Section: B: Infinity Fabric Intersocket (Ifis)mentioning

confidence: 99%

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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“…Thus, designers often optimize QoR by tuning various LSPD parameters using Phase-1 QoR metrics as guidance in a process also referred to as design-space exploration (DSE). 3 After the Phase-1 DSE, the second phase of the LSPD flow is executed to produce the final physical layout. Our target LSPD tool-chain provides about 400 binary parameters, which act as meta-parameters.…”

Section: Recommender System Overviewmentioning

confidence: 99%

“…As an example of iterative parameter tuning employed for prior processors, we consider the design of a double-precision floatingpoint pipeline macro. This macro contains 75, 000 logic gates and takes 8 hours on average to be processed through the LSPD flow when deployed in an industrial environment targeting a 14nm semiconductor technology process (similar to the processes used in [3,5,21]). During 5 iterations of the parameter tuning process, 173 LSPD scenarios with different parameter configurations have been applied, i.e., each iteration included parallel execution of multiple scenarios.…”

Section: Recommender System Overviewmentioning

confidence: 99%

“…The main computing engine of any modern computer server is a high-performance processor realized as a very-large-scale integration (VLSI) circuit. State-of-the-art systems-on-chips host billions of transistors on a single chip [3,5,21]. Such outstanding computational capabilities have been enabled by the progress of computer-aided design (CAD) tools for logic synthesis and physical design (LSPD), which have allowed hardware designers to cope with the remarkably growing complexity of VLSI design.…”

Section: Introductionmentioning

confidence: 99%

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A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors

Kwon

Ziegler

Carloni

2019

Proceedings of the 56th Annual Design Automation Conference 2019

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Logic synthesis and physical design (LSPD) tools automate complex design tasks previously performed by human designers. One timeconsuming task that remains manual is configuring the LSPD flow parameters, which significantly impacts design results. To reduce the parameter-tuning effort, we propose an LSPD parameter recommender system that involves learning a collaborative prediction model through tensor decomposition and regression. Using a model trained with archived data from multiple state-of-the-art 14nm processors, we reduce the exploration cost while achieving comparable design quality. Furthermore, we demonstrate the transfer-learning properties of our approach by showing that this model can be successfully applied for 7nm designs.

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Development of benchmark automation suite and evaluation of various high-performance computing systems

et al. 2020

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‘Zeppelin’: An SoC for multichip architectures

Cited by 67 publications

References 1 publication

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors

Development of benchmark automation suite and evaluation of various high-performance computing systems

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