Yield considerations in the choice of 3D technology

Smith, Greg; Smith, Larry; Hosali, Sharath; Arkalgud, Sitaram

doi:10.1109/issm.2007.4446880

Cited by 34 publications

(23 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For the yield improvement of 3D ICs, a number of researches proposed wafer or die matching methodologies to maximize functional yield, parametric yield, and the corresponding profits [16][17][18]. Smith et al [16] showed the yield trend of 3D ICs compared to 2D ICs and an idea to improve the functional yield of wafer-to-wafer bonded 3D ICs by choosing wafer pairs whose patterns of working dies best match each other.…”

Section: Introductionmentioning

confidence: 99%

“…Smith et al [16] showed the yield trend of 3D ICs compared to 2D ICs and an idea to improve the functional yield of wafer-to-wafer bonded 3D ICs by choosing wafer pairs whose patterns of working dies best match each other. Reda, Smith, and Smith [17] proposed wafer assignment algorithms to maximize the functional yield of 3D stacked ICs in wafer-to-wafer integration.…”

Section: Introductionmentioning

confidence: 99%

“…The work in [18] needs a critical path model representing the whole system behavior. Importantly, the aforementioned 3D yield improvement works [16][17][18] did not consider different timing behavior of the 3D clock network compared to the 2D one. Moreover, 3D yield analysis works in [1][2][3] using the averaging effect of variation on data path can be more meaningful when we guarantee correct clock signal arrival under a tolerable 3D clock skew budget.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

Kim¹,

Kim²

2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

Kim¹,

Kim²

2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…Wafer matching has been researched to mitigate this drawback by many authors [17,20,21,24,27]; it is a technique based on the matching of wafers with similar fault maps. In case of a large stack size or low die yield, the improvement can be significant.…”

Section: W2w Matchingmentioning

confidence: 99%

“…Improve yield for 3D circuits based on wafer matching has been discussed by many authors [17,20,21,24,27]. In this paper, we use the adaptive Best Pair (BP) algorithm [24] to determine the yield increase due to wafer matching.…”

Section: Yield and Cost Models For Wafer Matchingmentioning

confidence: 99%

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Taouil

Hamdioui

2012

J Electron Test

View full text Add to dashboard Cite

Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the tradeoff between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.

show abstract

Testing 3D Stacked ICs Containing Through-Silicon Vias

Marinissen¹

2010

Integrated Circuits and Systems

View full text Add to dashboard Cite

Yield considerations in the choice of 3D technology

Cited by 34 publications

References 3 publications

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Testing 3D Stacked ICs Containing Through-Silicon Vias

Contact Info

Product

Resources

About