Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product

Chen, Chen; Xiang, Xiaoyan; Liu, Chang; Shang, Yunhai; Guo, Ren; Liu, Dongqi; Lu, Yimin; Hao, Ziyi; Luo, Jun; Chen, Zhijian; Li, Chunqiang; Pu, Yu; Meng, Jianyi; Yan, Xiao; Xie, Yuan; Qi, Xiaoning

doi:10.1109/isca45697.2020.00016

Cited by 70 publications

(37 citation statements)

References 18 publications

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“…Furthermore, the comparison in this work omits proprietary implementations, namely the RV64GC multi-core within the PolarFire SoC (Microsemi, [9]), customized A25 and AX25 SoCs (Andes Technology, [1]), the SCR5 and SCR7 (Syntacore, [11]), several core complexes from CloudBear [3], and the Bk7 from Codasip [4]. T-head of the Alibaba Group claims to outperform any other RISC-V implementation with its XuanTie-910 processor [20]; however, it is also not available as open source.…”

Section: Analysis Of Risc-v Implementationsmentioning

confidence: 99%

A comparative survey of open-source application-class RISC-V processor implementations

Dorflinger

Albers

Kleinbeck

et al. 2021

Proceedings of the 18th ACM International Conference on Computing Frontiers

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The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology. CCS CONCEPTS• Computer systems organization → System on a chip; Serial architectures.

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Section: Analysis Of Risc-v Implementationsmentioning

confidence: 99%

A comparative survey of open-source application-class RISC-V processor implementations

Dorflinger

Albers

Kleinbeck

et al. 2021

Proceedings of the 18th ACM International Conference on Computing Frontiers

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show abstract

“…The goal of RISC-V is to become a general instruction set architecture. RISC-V has been used in low-power Internet of Things [108], storage controllers [4,109], artificial intelligence machine learning [110][111][112], wireless sensor networks, data centers [113], high-performance computing [114], and many other application scenarios. Table 1 lists the representative RISC-V boards on the market, and summarizes the processor models, security features, and target application scenarios.…”

Section: Security Requirements Of General Platformsmentioning

confidence: 99%

A Survey on RISC-V Security: Hardware and Architecture

2021

Preprint

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The Internet of Things (IoT) is an ongoing technological revolution. Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA). In recent years, the free and open RISC-V ISA standard has attracted the attention of industry and academia and is becoming the mainstream. Many companies have already owned or are designing RISC-V processors. Many important operating systems and major tool chains have supported RISC-V. Data security and user privacy protection are common challenges faced by all IoT devices. In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices is not tampered with or leaked. Many RISC-V security research projects are underway, but the academic community has not yet conducted a comprehensive survey of RISC-V security solutions. The latest technology and future development direction of RICS-V security research are still unclear. In order to fill this research gap, this paper presents an in-depth survey on RISC-V security technologies. This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Specifically, we first briefly introduce the background and development status of RISC-V, and compare the RISC-V mechanisms with the most relevant Arm mechanisms, highlighting their similarities and differences. Then, we investigate the security research of RISC-V around the theme of hardware and architecture security. Our survey covers hardware and physical access security, hardware-assisted security units, ISA security extensions, memory protection, cryptographic primitives, and side-channel attack protection. Based on our survey, we predict the future research and development directions of RISC-V security. We hope that our research can inspire RISC-V researchers and developers.CCS Concepts: • Security and privacy → Embedded systems security; Cryptography.

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“…Blocking instructions are also supported with minor modification. CAS cas0(clk, net[0], net [1], net [4], net [5]); 29 CAS cas1(clk, net[2], net [3], net [6], net [7]); 30 31 CAS cas2(clk, net [4], net [7], net [8], net [11]); 32 CAS cas3(clk, net [5], net [6], net [9], net [10]); 33 34 CAS cas4(clk, net [8], net [9], net [12], net [13]); 35 CAS cas5(clk, net [10], net [11], net [14], net [15]); 36 37 // Assigning input and output to wires in the sorting network 38 // (only using 1 input and 1 output reg. for this instruction) 39 for (i=0; i<4; i=i+i) assign net[i]=in_vdata1[32*(i+1)-1-:32]; 40 assign out_vdata1={net [12], net [13], net [14], net [15]}; The example instruction implementation in Algorithm 1 is a bitonic sorter of 4 inputs.…”

Section: Instruction Templatesmentioning

confidence: 99%

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

Papaphilippou,

Kelly,

Luk

2021

Preprint

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This paper presents a novel, non-standard set of vector instruction types for exploring custom SIMD instructions in a softcore. The new types allow simultaneous access to a relatively high number of operands, reducing the instruction count where applicable. Additionally, a high-performance open-source RISC-V (RV32 IM) softcore is introduced, optimised for exploring custom SIMD instructions and streaming performance. By providing instruction templates for instruction development in HDL/Verilog, efficient FPGA-based instructions can be developed with few low-level lines of code. In order to improve custom SIMD instruction performance, the softcore's cache hierarchy is optimised for bandwidth, such as with very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications on an FPGA. Although the exploration is based on the softcore, the goal is to provide a means to experiment with advanced SIMD instructions which could be loaded in future CPUs that feature reconfigurable regions as custom instructions. Finally, we provide some insights on the challenges and effectiveness of such future micro-architectures.

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Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product

Cited by 70 publications

References 18 publications

A comparative survey of open-source application-class RISC-V processor implementations

A comparative survey of open-source application-class RISC-V processor implementations

A Survey on RISC-V Security: Hardware and Architecture

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

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