Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

Abstract

This paper presents a novel, non-standard set of vector instruction types for exploring custom SIMD instructions in a softcore. The new types allow simultaneous access to a relatively high number of operands, reducing the instruction count where applicable. Additionally, a high-performance open-source RISC-V (RV32 IM) softcore is introduced, optimised for exploring custom SIMD instructions and streaming performance. By providing instruction templates for instruction development in HDL/Verilog, efficient FPGA-based instructions can be developed with few low-level lines of code. In order to improve custom SIMD instruction performance, the softcore's cache hierarchy is optimised for bandwidth, such as with very wide blocks for the last-level cache. The approach is demonstrated on example memory-intensive applications on an FPGA. Although the exploration is based on the softcore, the goal is to provide a means to experiment with advanced SIMD instructions which could be loaded in future CPUs that feature reconfigurable regions as custom instructions. Finally, we provide some insights on the challenges and effectiveness of such future micro-architectures.

Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions

“…Custom instruction templates are provided inside the softcore codebase for adding low-level user code for SIMD instruction implementations in Verilog [17].…”

“…In this paper, we present an open-source RISC-V softcore [17] that is optimised for exploring custom SIMD instructions. In order to achieve high throughput for streaming applications, the focus was given on the cache hierarchy and communication.…”