Xception: a technique for the experimental evaluation of dependability in modern computers

Carreira, João; Madeira, Henrique; Silva, João Gabriel

doi:10.1109/32.666826

Cited by 303 publications

(110 citation statements)

References 32 publications

(31 reference statements)

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“…For such cases generic workloads are typically used. Examples include standard performance benchmark applications Kanawati et al, 1992;Carreira et al, 1998]. The same problem arises when testing components, which may be reused in the future.…”

Section: Test Applicationsmentioning

confidence: 99%

“…This translates into a reduction of injections by 49.8% in total compared to the full set used previously. Some fault injection tools support such specification of injections, like Xception [Carreira et al, 1998]. …”

Section: Distinguishing Control Vs Datamentioning

confidence: 99%

“…Many fault injection tools support both event and time-triggered injection [Carreira et al, 1998;Kanawati et al, 1995], but still leaves the burden of choosing events and/or distributions to the user.…”

Section: Time-triggermentioning

confidence: 99%

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Robustness Evaluation of Operating Systems

Johansson

2008

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SummaryThe premise behind this thesis is the observation that Operating Systems (OS), being the foundation behind operations of computing systems, are complex entities and also subject to failures. Consequently, when they do fail, the impact is the loss of system service and the applications running thereon. While a multitude of sources for OS failures exist, device drivers are often identified as a prominent cause behind failures.In order to characterize the impact of driver failures, at both the OS and application levels, this thesis develops a framework for error propagation-based robustness profiling for an OS. The framework is first developed conceptually and then experimentally validated on a real OS, namely Windows CE .Net. The choice of Windows CE is driven by its representativeness for a multitude of OS's, as well as the ability to customize the OS components for particular needs.For experimental validation, fault injection is a prominent technique that can be used to simulate faults (or errors) in the system by inserting synthetic ones and study their effect. Three key questions with such a technique are where, what and when to inject faults. This thesis shows how injecting errors at the interface between drivers and the OS can be very effective in evaluating the effects driver faults can have.To quantify the OS's robustness, this thesis defines a series of error propagation measures, specifically tailored for device drivers. These measures allow for quantifying and comparing both individual services and device drivers on their susceptibility and diffusing abilities.This thesis compares three contemporary error models on their suitability for robustness evaluation. The classical bit-flip model is found to identify a higher number of severe failures in the system. It also identifies failures for more services than both other models, data type and fuzzing. However, its main drawback is that it requires substantially more injections than the other two. Fuzzing, even though not giving rise to as many failures is able to find new additional services with severe failures.A careful study of the injections performed with the bit-flip model shows that only a few bits are generally useful for identifying new services with robustness weaknesses. Consequently, a new composite model is proposed, combining the most effective bits of the bit-flip model with the fuzzing model's ability to identify new services, giving rise to new model without loss of important information and at the same time incurring a moderate number of injections.To answer the question of when to inject an error this thesis proposes a novel model of a driver's usage profile, focusing on high-level operations being carried out. It guides the injection of errors to instances when the driver is carrying out specific operations. Results from extensive fault injection experiments show that more service vulnerabilities can be discovered. Furthermore, a priori profiling of the drivers can show how effective the proposed approach will be. vi

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Section: Test Applicationsmentioning

confidence: 99%

Section: Distinguishing Control Vs Datamentioning

confidence: 99%

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Robustness Evaluation of Operating Systems

Johansson

2008

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“…Although a significant amount of research has resulted in software simulation methods [1], [5], [22], [11], these tools are not powerful enough to simulate entire SoCs running real applications such as the probabilistic filters reported here. Radiation testing [27], [29] can provide insight but requires access to a radiation testing facility and non-trivial conversion of the error rates observed [16].…”

mentioning

confidence: 99%

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors

Sauer

Tomashevich

Müller

et al. 2011

2011 IEEE 17th International on-Line Testing Symposium

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Abstract-State-of-the-art cyber-physical systems are increasingly deployed in harsh environments with non-negligible soft error rates, such as aviation or search-and-rescue missions. State-of-the-art nanoscale manufacturing technologies are more vulnerable to soft errors. In this paper, we present an FPGAbased framework for injecting soft errors into user-specified memory elements of an entire microprocessor (MIPS32) running application software. While the framework is applicable to arbitrary software, we demonstrate its usage by characterizing soft errors effects on several software filters used in aviation for probabilistic sensor data fusion.

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“…However, FERRARI waits for a timer interrupt to inject errors, where execution time would be shifted if there is any resource sharing contentions. Xception, proposed in [13], requires dedicated hardware support of debugging register. AFI only relies on commonly available features from operating system and processor hardware, therefore can be adapted to a broad platform.…”

Section: Related Workmentioning

confidence: 99%

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

Wang¹

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As the semiconductor industry keeps evolving at the pace predicted by Moore's Law, computer system architects are facing increasing challenges from the three major design constraints: performance, power, and reliability. Thermal constraints from a reasonable cooling cost do not scale well as technology evolves. The dwindling scaling on threshold voltage leads to a slower pace of supply voltage scaling. These two effects lead to an increasing power density in current and future technology generations. Reliability has emerged as a primary design constraint due to the smaller feature size and generally lower supply voltage for electronic devices. Transient errors caused by high-energy particle strike and voltage noises are expected to increase significantly in frequency.Performance improvement becomes more challenging for future architectures with limitations set by the power and the resilience constraints.Integration of accelerators to create heterogeneous processors is becoming more common for both power and performance reasons. However, this adds one more dimension to the design space that is already complex due to technology variants, system organizations, application's variability, and so on. Therefore, high-level models are essential for system designers to explore the design space and make decisions in a timely manner. Additionally, the three design constraints compete with each other. For example, resilience-aware techniques, such as DMR and TMR, are expensive in terms of power and performance, low-power designs usually come with a price of lower speed.Consequently, it requires system designers to make trade-offs by considering all the three design constraints at the same time.To address these challenges, we (1) propose an analytical modeling framework called Lumos that is capable of modeling power and performance for heterogeneous architectures with hardware iv v accelerators. Then we (2) use Lumos to explore the design space composed of CPU cores and accelerators, revealing important scaling trend for future heterogeneous architectures. We further (3) propose a rapid modeling framework to characterize resilience across a range of applications in DSP, and image processing domains; And finally we (4) propose an integrated framework to optimize energy-efficiency by trading off design constraints of power, performance and resilience. Acknowledgments

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Xception: a technique for the experimental evaluation of dependability in modern computers

Cited by 303 publications

References 32 publications

Robustness Evaluation of Operating Systems

Robustness Evaluation of Operating Systems

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

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