Write-optimized reliable design of STT MRAM

Kim, Yusung; Gupta, Sumeet Kumar; Park, Sang Phill; Panagopoulos, Georgios; Roy, Kaushik

doi:10.1145/2333660.2333664

Cited by 63 publications

(27 citation statements)

References 8 publications

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“…The dynamic energy is not ignorable for some workloads such as WD4 and the leakage energy is mainly consumed by the global peripheral circuits for many workloads. However, they can be significantly reduced by the previous works such as [12], [15], [20].…”

Section: B Experimental Resultsmentioning

confidence: 99%

“…RELATED WORK In contrast to state-of-the-art STT-MRAM caches, the write-access energy had been the most significant problem in STT-MRAM caches. Based on this observation, many architectural techniques for its reduction have been proposed [3], [12], [15]. Wu et al propose a cache system that is composed of STT-MRAM and SRAM area [3].…”

Section: B Experimental Resultsmentioning

confidence: 99%

“…To drive large write current, large and leaky transistors are required for peripheral circuits in STT-MRAM caches [12]. First of all, the cell transistor shown in Figure 1 must be designed with enough drive ability margin, thus it must be large [6].…”

Section: Background a Leakage Problem In Stt-mram Cachesmentioning

confidence: 99%

“…The impact of write energy is also large for some workloads such as WD4, however it can be reduced by the existing techniques such as EWT (Early Write Termination) [15]. Thus, we need to focus on reduction of leakage energy of STT-MRAM caches, though the write access energy has been regarded as the most critical problems [3], [12], [15], [16]. Figure 3 presents the leakage power breakdowns of an 1MB SRAM LLC and a 2MB STT-MRAM LLC which have the same area.…”

Section: B Quantification Of Leakage Impact Of Stt-mram Cachesmentioning

confidence: 99%

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Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches

Arima

Noguchi

Nakada

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer from leakage power because large and leaky transistors are required to drive large write current to STT-MRAM element. To overcome this problem, we propose a new power management scheme called Immediate Sleep (IS). IS immediately turns off a subarray of an STT-MRAM cache if the next access is predicted to be not critical in performance. Thus, IS can effectively reduce leakage energy with little impact on performance. Our experimental results show that our technique can save the leakage energy of an STT-MRAM LLC by 32% compared to an STT-MRAM LLC with the conventional scheme at the same performance.

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Section: B Experimental Resultsmentioning

confidence: 99%

Section: B Experimental Resultsmentioning

confidence: 99%

Section: Background a Leakage Problem In Stt-mram Cachesmentioning

confidence: 99%

Section: B Quantification Of Leakage Impact Of Stt-mram Cachesmentioning

confidence: 99%

See 2 more Smart Citations

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches

Arima

Noguchi

Nakada

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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“…The stronger source degeneration in 1T1R cells causes much stronger write asymmetry and results in wasted write energy 21 . It is also noted that in 1T1R bit-cell design, boosted voltage (i.e.…”

Section: ) Results and Discussionmentioning

confidence: 99%

DSH-MRAM: Differential Spin Hall MRAM for On-Chip Memories

Kim

Choday

Roy

2013

IEEE Electron Device Lett.

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A new device structure for spin transfer torque based magnetic random access memory is proposed for on-chip memory applications. Our device structure exploits spin Hall effect to create a differential memory cell that exhibits fast and energy-efficient write operation.Moreover, due to inherently differential device structure, fast and reliable read operation can be performed. Our simulation study shows 10X improvement in write energy over the standard 1T1R STT-MRAM memory cell, and 1.6X faster read operation compared to single-ended sensing (as in standard 1T1R STT-MRAMs). The bit-cell characteristics are promising for high performance on-chip memory applications.

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Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories

Monazzah

Rahmani

Miele

et al. 2020

Dependable Embedded Systems

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Due to the consistent pressing quest of larger on-chip memories and caches of multicore and manycore architectures, Spin Transfer Torque Magnetic RAM (STT-MRAM or STT-RAM) has been proposed as a promising technology to replace classical SRAMs in near-future devices. Main advantages of STT-RAMs are a considerably higher transistor density and a negligible leakage power compared with SRAM technology. However, the drawback of this technology is the high probability of errors occurring especially in write operations. Such errors are asymmetric and transition-dependent, where 0 → 1 is the most critical one, and is high subjected to the amount and current (voltage) supplied to the memory during the write operation. As a consequence, STT-RAMs present an intrinsic trade-off between energy consumption vs. reliability that needs to be properly tuned w.r.t. the currently running application and its reliability requirement. This chapter proposes FlexRel, an energy-aware reliability improvement architectural scheme for STT-RAM cache memories. FlexRel considers a memory architecture provided with Error Correction Codes (ECCs) and a custom current regulator for the various cache ways and conducts a trade-off between reliability and energy consumption. FlexRel cache controller dynamically profiles the number of 0 → 1 transitions of each individual bit write operation in a cache block and based on that selects the most-suitable cache way and current level to guarantee the necessary error rate threshold (in terms of occurred write errors) while minimizing the energy consumption. We experimentally evaluated the efficiency of FlexRel against the most efficient uniform protection scheme from reliability, energy, area, and performance perspectives. Experimental simulations performed by using gem5 has demonstrated that while FlexRel satisfies the given error rate threshold, it delivers up to 13.2% energy saving. From the area footprint perspective, FlexRel delivers up to 7.9% cache ways’ area saving. Furthermore, the performance overhead of the FlexRel algorithm which changes the traffic patterns of the cache ways during the executions is 1.7%, on average.

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Write-optimized reliable design of STT MRAM

Cited by 63 publications

References 8 publications

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches

DSH-MRAM: Differential Spin Hall MRAM for On-Chip Memories

Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories

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