Worst-case static noise margin criteria for logic circuits and their mathematical equivalence

Lohstroh, J.; Seevinck, E.; Groot, John de

doi:10.1109/jssc.1983.1052035

Cited by 183 publications

(76 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The issue of the reliability of logic memory elements has been always related to the definition of noise margins. In SRAM cells, the criterion of maximum squares in the mirrored VTCs [15] has been applied to quantify nominal static noise margins [19], which express the stability of the memory element to internal voltage noise during idle mode, read access and write access. SRAM cell stability has been studied in terms of such static noise margins with respect to process variations [26] and to NBTI aging [6].…”

Section: Background and Related Workmentioning

confidence: 99%

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

Khalid

Mastrandrea

Olivieri

2015

Microelectronics Reliability

View full text Add to dashboard Cite

Section: Background and Related Workmentioning

confidence: 99%

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

Khalid

Mastrandrea

Olivieri

2015

Microelectronics Reliability

View full text Add to dashboard Cite

“…Since the publication of the original paper on static noise margins by Hill [12], there have been several papers dealing with the static and dynamic noise margins of logic circuits [13], [14] and memory cells [15]. Instead of using this work as a starting point, we choose to begin at first principles.…”

Section: Noise Stability As a Metric For Noise Immunitymentioning

confidence: 99%

“…and are the transfer functions of gates I and II, i.e., and . The latch will be stable in the presence of the series-voltage dc noise sources ( and ) on evaluation nodes and , if at the bias point determined by these sources [13], [14] (2)…”

Section: B Noise Stabilitymentioning

confidence: 99%

See 1 more Smart Citation

Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits

Singh¹

2009

Signal Integrity Effects in Custom IC and ASIC Designs

View full text Add to dashboard Cite

Abstract-As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systematically on a full-chip basis using simulationbased transistor-level analysis. We then describe Harmony, a two-level (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reduced-order modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be used to limit pessimism in the analysis.Index Terms-Deep-submicron IC's, interconnect coupling, signal integrity, static noise analysis.

show abstract

“…1). This mode of circuit operation translates into a requirement of 3 distinct roots of the Static voltage characteristics of cell storage nodes [13][14]. During a Write operation (Fig.…”

Section: Introductionmentioning

confidence: 99%