Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor

Enhancing the L1 Data Cache Design to Mitigate HCI

“…Results were gathered just for the memory cell with the highest number of flips (not necessarily the same cell across the studied approaches), which is the one that suffers the highest HCI wearout. Results have been computed using a standard dV th formula [8] and assuming a 3-year lifetime for our 32nm technology node [3]. To complete this execution period, we have assumed that the simulated amount of 500M instructions is repeated over and over until the established period is reached.…”

A cross-layer SER analysis in the presence of PVTA variations

“…Transistor aging due to HCI is deeply investigated in [32,69]. The authors of [19] proposed a novel instance-based BTI analysis technique. Library-based and LUT-based aging techniques are presented in [69,68,19,70,30].…”

“…Process, Voltage, Temperature, and Aging (PVTA) variation is one of the major dark sides of the technology scaling [19][20][21][22][23][24]. Due to the process variations [25,26] attributes of transistors (such as gate length, oxide thickness, diffusion depth, and V th variation mainly because of random dopant fluctuation) deviate from their nominal value.…”

Reliability and Aging Analysis on SRAMs Within Microprocessor Systems

“…However, the realistic stress conditions of the SRAM cells really depend on customer usages (workload). In [10][11][12][13], the authors estimated the SRAM degradation due to BTI based on the realistic stress conditions considering the actual workload. On the other hand, the impact of the HCI effect on SRAM stability is not as studied as BTI because BTI is usually dominant due to its frequency independence.…”