WL-Reviver: A Framework for Reviving any Wear-Leveling Techniques in the Face of Failures on Phase Change Memory

Abstract

Abstract-While Phase Change Memory (PCM) has emerged as one of most promising complements or even replacements of DRAM-based memory, it has only limited write endurance. Because of uneven write distribution, PCM is highly likely to have early failures, which can spread over the chip space and leave the entire chip unusable. Wear leveling is an indispensable technique to even out wear caused by the writes. However, because of process variation early failure cannot be fully avoided. State-of-the-art wear-leveling schemes, such as Start-Gap and Security Refresh, cease to function once even a single block failure occurs because their designs require persistent writable address space for wear leveling operations. Existent solutions attempting to address the problem demand substantial OS supports, such as explicit space allocations and data migrations. The demand on substantial OS cooperation creates a barrier to widespread adoption of the PCM technique.While fault-tolerance techniques, such as FREE-p and zombie, that remap failed blocks to inaccessible but healthy space have the potential to address the wear-leveling issue by relocating data from failed blocks to healthy ones, they cannot work together with the wear-leveling schemes as data migration may change placement of relocated data. In this paper, we propose a framework, WL-Reviver, that allows any in-PCM wear-leveling scheme to keep delivering its designed leveling service even after failures occur in its working address space. The design is unique on two aspects: (1) it leverages the fault-tolerance techniques so that they can work together with the wearleveling schemes; and (2) it requires no OS supports additional to what're available to today's DRAM-based memory system. Furthermore, WL-Reviver is a lightweight framework of very low overhead. Our extensive experiments show that WLReviver can efficiently revive a wear-leveling scheme without compromising the scheme's wear-leveling effect.

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

“…Thus, they proposed nCode, which exploits NVRAM's byte addressable to execute the code page directly in the swap area, without being swapped back to main memory, further improving the endurance of NVRAM. Fan et al [2014] proposed WL-Reviver, a framework that allows any in-PCM wearleveling scheme to keep delivering its designed leveling service even after failures occur in its working address space. WL-Reviver is a lightweight framework with very low overhead, which can efficiently revive a wear-leveling scheme without compromising the wear-leveling effect of this scheme.…”

WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders

“…State-of-the-art fault tolerance techniques [5,26,35,81,87,89,113] do not discuss how wear-leveling can continue operating seamlessly after a failed memory block is mapped out. Once a block fails, the assumption that any address can be remapped to any other address is no longer valid [25]. One way to solve this problem is to detect mapped-out locations by checking failures in the read-after-write veri cation process.…”

“…Although SR is not able to handle wear-leveling after mapping out memory pages, we assume it can continue its operation. This requires applying additional resources to make the combined SR+ECP k work [25], whose overheads we do not account for so that we give the bene t of doubt to SR.…”

“…Wear-Leveling Techniques for PCM. There are many prior works that propose wear-leveling techniques to enhance PCM lifetime [2,[21][22][23]25,29,34,41,61,62,77,82,83,88,95,116,117,[120][121][122]. These works propose di erent techniques to optimize wear-leveling via swapping and remapping data.…”

“…Unfortunately, to our knowledge, there is no technique that combines both wear-leveling and fault tolerance techniques in a seamless way to 1) level out the write non-uniformity and 2) tolerate faults when memory cells reach their endurance limits. A previous work [25] shows that naively combining both techniques can result into the malfunction of the system: a commonly-used wear-leveling technique stops working seamlessly once the rst data block fails and is mapped out, since the data block's physical position becomes unavailable as a remapping target [25].…”