Wire bond degradation under thermo- and pure mechanical loading

Pedersen, Kristian Bonderup; Nielsen, Dennis; Czerny, Bernhard; Khatibi, Golta; Iannuzzo, Francesco; Popok, Vladimír; Pedersen, Kjeld

doi:10.1016/j.microrel.2017.07.055

Cited by 14 publications

(9 citation statements)

References 11 publications

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“…where da/dN is the propagation rate per cycle, C and m are the Paris' constants and ∆K is the stress intensity factor variation. Based on this law, it can be expected that the crack development will also follow a power law with a certain m. This tendency was earlier found for the same type of devices as in this work but subjected to passive thermal cycling [16].…”

Section: Resultssupporting

confidence: 81%

“…One of them is a passive thermal cycling, where the components of power modules are subjected to varying temperature on a short time scale without applying electric power [13,14], thus, mimicking active power cycling but only in terms of thermalinduced stresses. Another approach suggests to utilize mechanical cycling of wire bonds in order to originate the stresses similar to those caused by the thermal-induced ones [15][16][17]. This mechanical cycling can be carried out at high frequencies reducing the test period to seconds and, thus, making it very attractive for reliability analysis.…”

Section: Introductionmentioning

confidence: 99%

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Comparative study of wire bond degradation under power and mechanical accelerated tests

Popok

Buhrkal-Donau

Czerny

et al. 2019

J Mater Sci: Mater Electron

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Degradation of wire bonds under accelerated power cycling tests is compared to that caused by mechanical high-frequency cycling for commercial power devices. Using micro-sectioning approach and optical microscopy it is found that the bond fracture under the mechanical cycling follows the same tendencies as that found under power cycling. Results of shear tests of the mechanically cycled bonds also agree well with the bond cracking tendencies observed by optical microscopy investigations. It is found that reduction of contact area of the wire at the bond/metallization interface due to the crack development follows the Paris-Erdogan law, which defines the degradation rate leading to wire lift-off.The results obtained on mechanical cycling in the current work also show good agreement with literature data on wire bond fracture under power cycling proving that main mechanism for wire lift-off failure is related to the mechanical stress development at the interface with metallization layer. The carried out study also creates a potential to further develop a high-frequency mechanical cycling into an alternative for reliability analysis of wire bonds. However, more studies have to be performed to compare degradation mechanisms occuring under power and mechanical accelerated tests.

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Section: Resultssupporting

confidence: 81%

Section: Introductionmentioning

confidence: 99%

Comparative study of wire bond degradation under power and mechanical accelerated tests

Popok

Buhrkal-Donau

Czerny

et al. 2019

J Mater Sci: Mater Electron

View full text Add to dashboard Cite

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“…The FIDES methodology is based on physics-of-failure models and supported by the analysis of different stresses such as temperature and humidity from the field returns, however, the models are generic and limited to a few number of components [4]. Furthermore, the device manufactures have proposed reliability models based on accelerated aging tests, such as power cycling [5] and temperature cycling under constant load profiles [6], neglecting the real mission profile. As a consequence, many reliability engineers are in need to run power cycling tests at different operating conditions (t on , I load , T j , and ∆T j ) [7]- [11].…”

Section: Introductionmentioning

confidence: 99%

“…With the results from these tests, it is possible to estimate the lifetime of the component based on the application requirements and the type of power semiconductor package (i.e. gelfilled [6], molded modules [8], single or multi-chip modules [11]). A more accurate reliability estimation method for power semiconductors are those approaches taking into account the mission profiles (i.e., wind speed, ambient temperature, solar irradiance, etc) [12]- [14], in order to estimate the real thermomechanical stress at the solder layer or bond wire interface [15].…”

Section: Introductionmentioning

confidence: 99%

Implications of Ageing Through Power Cycling on the Short-Circuit Robustness of 1.2-kV SiC mosfets

Reigosa

Luo

Iannuzzo

2019

IEEE Trans. Power Electron.

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In this paper, the reliability performance of 1.2-kV SiC power MOSFET modules is investigated through the combination of both accelerated power cycling tests and short circuit tests. The short-circuit robustness of SiC MOSFETs is investigated after stressing the dies under power cycling tests. In this way, the implications of different levels of degradation on the short circuit capability can be better understood. During the power cycling tests, some electrical parameters, either related to the package or the die, may experience variations as a consequence of the device ageing (e.g., increase in bond wire resistance and increase in gate leakage current). The effect of these parameter variations on the short-circuit withstanding capability of SiC MOSFETs is investigated for the first time in this work. The proposed method helps to understand which degradation effects under normal operation have a major implication on the short-circuit robustness, which gives a more realistic information about the root cause of the failures observed in the field.

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“…At system level, an appropriate package for these devices is required to maximize the power converter performances. The main weak points of the standard packaging and interconnection technologies are the wire bondings on the topside contacts and the solder materials on the backside contact [2][3][4]. Offering an alternative solution for one or both, the top and backside contacts, is motivating recent developments and researches in power electronics packaging in order to improve the electrical, thermal, thermomechanical and EMC performances of the power modules.…”

Section: Introductionmentioning

confidence: 99%

Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics

Vladimirova

Widiez

Letowski

et al. 2018

2018 IEEE 68th Electronic Components and Technology Conference (ECTC)

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This paper presents a wafer-level pre-packaging technology for power devices. The concept consists in the implementation of a thick 3D patterned copper leadframe ensuring the interconnections of the power devices among them or with the other components of the converter. The metallic leadframe is bonded between two wafers of semiconductor devices enabling the 3D power module integration by the 3D stacking of one or multiple switching cells. Specific technology developments are introduced, practical realizations of the concept are presented and the electrical characterizations of the first prototypes are discussed.

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Wire bond degradation under thermo- and pure mechanical loading

Cited by 14 publications

References 11 publications

Comparative study of wire bond degradation under power and mechanical accelerated tests

Comparative study of wire bond degradation under power and mechanical accelerated tests

Implications of Ageing Through Power Cycling on the Short-Circuit Robustness of 1.2-kV SiC mosfets

Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics

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