WIPAL: Window-based parallel layout decomposition in double patterning lithography

Yao, Hailong; Cai, Yici; Zhao, Wei

doi:10.1109/icsict.2012.6466674

Cited by 4 publications

(4 citation statements)

References 27 publications

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“…Inspired by Refs. [7] and [14], we propose a bin-based library matching method to detect the NCs in TP coloring. Figure 2 shows the overall flow of our proposed method.…”

Section: Methodsmentioning

confidence: 99%

“…In DP lithography, the layout decomposition problem is essentially a two-color labeling problem and is often referred to as DP coloring. A lot of works have been done to minimizing the number of the conflicts and stitches simultaneously [2][3][4][5][6][7][8]. It should be noted that any existence of native conflict would result in layout re-design/modification.…”

Section: Fig 1 (A)mentioning

confidence: 98%

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Native conflict awared layout decomposition in triple patterning lithography using bin-based library matching method

Jiang

et al. 2016

SPIE Proceedings

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Triple patterning (TP) lithography becomes a feasible technology for manufacturing as the feature size further scale down to sub 14/10 nm. In TP, a layout is decomposed into three masks followed with exposures and etches/freezing processes respectively. Previous works mostly focus on layout decomposition with minimal conflicts and stitches simultaneously. However, since any existence of native conflict will result in layout re-design/modification and reperforming the time-consuming decomposition, the effective method that can be aware of native conflicts (NCs) in layout is desirable. In this paper, a bin-based library matching method is proposed for NCs detection and layout decomposition. First, a layout is divided into bins and the corresponding conflict graph in each bin is constructed. Then, we match the conflict graph in a prebuilt colored library, and as a result the NCs can be located and highlighted quickly.

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“…Inspired by Refs. [7] and [14], we propose a bin-based library matching method to detect the NCs in TP coloring. Figure 2 shows the overall flow of our proposed method.…”

Section: Methodsmentioning

confidence: 99%

Section: Fig 1 (A)mentioning

confidence: 98%

Native conflict awared layout decomposition in triple patterning lithography using bin-based library matching method

Jiang

et al. 2016

SPIE Proceedings

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“…A layout with many diagonal lines, jogs, and varying via sizes between layers will be complicated to split effectively. Several procedures and splitting rules are developed to handle different devices and design styles [20][21][22][23]. Apart from layout complexities, there are process control challenges of mask-tomask overlay alignment and critical dimension (CD) control for edges.…”

Section: Multiple Patterning Techniquementioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

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Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer-aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10-20 nm devices with ingenious interventions. The three-dimensional fin-shaped field-effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

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“…A layout with many diagonal lines, jogs, and varying via sizes between layers will be complicated to split effectively. Several procedures and splitting rules are developed to handle different devices and design styles [22][23][24][25]. Apart from layout complexities there are process control challenges of mask-to-mask overlay alignment and critical dimension control for edges.…”

Section: Double Patterning Techniquesmentioning

confidence: 99%

Critical Review of Current Trends in ASIC Writing and Layout Analysis

Vikram¹,

Agarwal

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Electrical Designs for Application SpecificIntegrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

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WIPAL: Window-based parallel layout decomposition in double patterning lithography

Cited by 4 publications

References 27 publications

Native conflict awared layout decomposition in triple patterning lithography using bin-based library matching method

Native conflict awared layout decomposition in triple patterning lithography using bin-based library matching method

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Critical Review of Current Trends in ASIC Writing and Layout Analysis

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