Wideband low-distortion delta-sigma ADC topology

Silva, J.; Moon, Un-Ku; Steensgaard, J.; Temes, Gábor C.

doi:10.1049/el:20010542

Cited by 483 publications

(224 citation statements)

References 1 publication

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“…It consists of a 1st-order Σ∆ modulator with a 3-level quantizer and an input feedforward branch. The input feedforward branch is needed to reduce the signal swing at the output node of the integrator (V out ) [7]. The threshold levels of the 3-level quantizer are determined in order to further reduce the swing at the output node of the integrator (V out ).…”

Section: A Principlementioning

confidence: 99%

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

Rombouts

Woestyn

Bock

et al. 2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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Abstract-We present a very compact analog-to-digital convertor (ADC) for use as a standard cell. To achieve an inherent accuracy of at least 12-bits without trimming or calibration, extended counting A/D-conversion is used. Here, the circuit performs a conversion by passing through two modes of operation: first it works as a 1st-order incremental convertor and then it is reconfigured to operate as a conventional algorithmic converter. This way, we obtain a Nyquist-rate converter that requires only 1 operational amplifier and achieves 12-bit accuracy performance in 13 clock cycles with 9 bit capacitor matching. The circuit is designed in 0.18 µm CMOS with a thick oxide option. The resulting analog core occupies a chip area of only 0.011 mm 2 and the complete digital control and reconstruction logic (including additional test features and storage registers) is 0.02 mm 2 . The analog blocks of the circuit consume 1.2mW and the digital 0.4mW. At a sample rate of 1 MS/s, the peak SNDR is 74.5dB and the dynamic range is 78dB, constant over the Nyquist band. The worst-case integral non-lineairity (INL) is within ±0.55 LSB.

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Section: A Principlementioning

confidence: 99%

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

Rombouts

Woestyn

Bock

et al. 2012

2012 Proceedings of the ESSCIRC (ESSCIRC)

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show abstract

“…quantisation noise, instead of the input signal. Consequently, the signal swing at the output of the LNA is dramatically reduced and is limited to one V LSB in a single-ended design, relaxing the linearity requirement of the LNA [4]. Moreover, the slew-rate requirement of the LNA is considerably mitigated owing to the reduced voltage swing.…”

Section: Event-driven Convertersmentioning

confidence: 99%

Low-distortion switched-capacitor event-driven analogue to-digital converter

2010

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An event-driven tracking analogue-to-digital converter (ADC) architecture is proposed. The proposed architecture has less sensitivity to amplifier and DAC nonlinearity, and reduces the swing and dynamic common-mode range requirement of the operational transconductance amplifier and comparators, respectively. The efficiency of the ADC is confirmed by detailed circuit simulations.Introduction: Emerging ultra-low-power applications such as wireless sensor networks and wireless body area networks require the integration of very efficient signal processing techniques, specifically in analogueto-digital conversion. General-purpose ADCs that rely on Nyquist theory result in unnecessary sampling, and dissipate excessive power within the ADC and subsequent digital signal processing units during periods of low activity. Activity dependent [1], variable resolution [2] ADCs, and continuous time digital signal processing [3] are the most recent techniques to tackle the aforementioned issues. This Letter presents an event-driven ADC architecture, which enables a significant relaxation of the analogue circuit specifications and improvement of the performance.

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“…In general, there are no specific constrains on the signal and noise transfer function of the first loop. To minimize the number of the DACs in the first loop, structures such as [4] can be used.…”

Section: Mash Versus Smashmentioning

confidence: 99%

Multi-loop efficient sturdy MASH delta-sigma modulators

Maghari

Moon

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards high order multi-loop modulators are discussed and a new multi-loop modulator is presented. This modulator benefits from a MASH architecture in the final loop to preserve stability, while the main loop benefits from relaxed circuit building blocks of the SMASH structure. Extensive simulation results are provided to prove the efficiency of this structure.

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Wideband low-distortion delta-sigma ADC topology

Cited by 483 publications

References 1 publication

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

Low-distortion switched-capacitor event-driven analogue to-digital converter

Multi-loop efficient sturdy MASH delta-sigma modulators

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