Wavefront technology mapping

Stok, Leon; Iyer, Mahesh A.; Sullivan, Andrew

doi:10.1109/date.1999.761178

Cited by 20 publications

(25 citation statements)

References 10 publications

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“…In the final step, the circuit is transformed into a fanout-free decomposition consisting of 2-input gates. Motivation: Traditionally, the algorithm [14] uses the arrival time at the input pins to create a delay optimal decomposition. In our layout aware approach, we include wiring delay based on the estimated net length and geographical location of the input signals.…”

Section: Decompositionmentioning

confidence: 99%

“…Our technology mapping algorithm is based on the concept of wavefront technology mapping as described in [14]. The wavefront algorithm traverses the network in a levelized order from the primary inputs to the outputs using a wavefront of specified width w. Within the width of the wavefront, bound by its head and tail, all possible technology matches are created and implemented, effectively creating multi-source nets.…”

Section: Technology Mappingmentioning

confidence: 99%

“…Due to the load-independent delay modeling in our gain-based delay model, a delay optimal technology implementation is created. We refer to [14] for a complete description of wavefront technology mapping under a gain-based delay model.…”

Section: Technology Mappingmentioning

confidence: 99%

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Congestion aware layout driven logic synthesis

Kutzschebauch¹,

Stok²

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

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In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure.In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.

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Section: Decompositionmentioning

confidence: 99%

Section: Technology Mappingmentioning

confidence: 99%

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Congestion aware layout driven logic synthesis

Kutzschebauch¹,

Stok²

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

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“…Logical effort [7,8] has been widely used in a variety of application domains [5,10,11,12] as well as in industry standard EDA synthesis tools [13,14]. Using logical effort, the delay of a gate with input capacitance c i is modeled by a linear function of the load c l as:…”

Section: Logical Effortmentioning

confidence: 99%

“…A number of algorithms have been proposed for this step, such as tree-mapping [1] and DAG-mapping [2], using load-dependent delay models [3], constant delay models [4,5] as well as using logical effort [6]. High-performance designs use rich libraries, with multiple instances of each cell, with varying delay, area and drive capabilities.…”

Section: Introductionmentioning

confidence: 99%

Logical effort based technology mapping

Karandikar

Sapatnekar

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

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EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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Wavefront technology mapping

Cited by 20 publications

References 10 publications

Congestion aware layout driven logic synthesis

Congestion aware layout driven logic synthesis

Logical effort based technology mapping

EDA in IBM: past, present, and future

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