Logical effort based technology mapping

Karandikar, S.K.; Sapatnekar, Sachin S.

doi:10.1109/iccad.2004.1382611

Cited by 13 publications

(8 citation statements)

References 16 publications

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“…Another area of application is in technology mapping, where circuits are broken into trees which are mapped individually, simply estimating the load values at the output of each tree. In [21], Delaycurves are used to determine the optimal assignment of loads at tree outputs, leading to superior mapped solutions.…”

Section: Discussionmentioning

confidence: 99%

Fast comparisons of circuit implementations

Karandikar

Sapatnekar

2005

IEEE Trans. VLSI Syst.

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Abstract-Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations-the minimum achievable delay and the cost of achieving a target delay-and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation.

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Section: Discussionmentioning

confidence: 99%

Fast comparisons of circuit implementations

Karandikar

Sapatnekar

2005

IEEE Trans. VLSI Syst.

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“…The basic mechanism used by the method presented here is that different transistor network topologies at the cell level can decrease the logical effort to compute a target logic function. Methods for mapping based on the logical effort have a first step of minimizing the logical effort before sizing [11]. The logical effort of a logic gate is the ratio of its input capacitance to that of one inverter that delivers equal output current.…”

Section: Logical Effortmentioning

confidence: 99%

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

Cardoso

Rosa

Marques³

et al. 2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs.

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“…There are methods that try to solve the problem of mapping and sizing simultaneously. The algorithm proposed by Karandikar (2004) is an example of it. It finds good results in polynomial time using more sophisticated delay models associated to some heuristics.…”

Section: Technology Mappingmentioning

confidence: 99%