Congestion aware layout driven logic synthesis

Abstract

In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times.With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure.In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.

PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking

“…Definition 1: Given gates s and d in the network, if there are more than one disjoint path from s to d, d is a reconvergent gate in the network [12].…”

Towards layout-friendly high-level synthesis

“…As interconnect problems become worse, it is insufficient to repair routability failures only during physical design. With the prevalence of RTL-based design flows, early interconnect estimation and optimization techniques during logic synthesis have been proposed, [24,25,27,31]. On the designer side, optimization of global interconnects is the central task of design planning and architecture definition.…”

Pre-layout wire length and congestion estimation

“…Layout-driven logic synthesis [12][17] [18] starts with creating an initial placement of the technologyindependent netlist and uses placement coordinates of the objects to improve the synthesis flow. Such methods work with very inaccurate placement model since final placement is likely to change substantially after synthesis.…”