2006 IFIP International Conference on Very Large Scale Integration 2006
DOI: 10.1109/vlsisoc.2006.313212
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PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking

Abstract: This paper describes an approximate approach for combinational equivalence checking. We propose an architecture such that a virtually-zero aliasing rate is obtained in a single-pass probability calculation. Furthermore, the aliasing rate can be easily configured in various precision by designers. We conduct experiments on a set of ISCAS'85 benchmarks. Experimental results show that with virtually-zero aliasing rate, for example, 10 −74 , our approach is more efficient than those exact approaches.

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Cited by 4 publications
(1 citation statement)
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“…In traditional equivalence checking [13] both circuits -CUT and the original circuit are available as white box. Hence, it is possible to use techniques like satisfiability solving [14] and randomized structural hashing [15], [16]. In contrast, the problem of trojan detection is more complicated since we only have the original circuit design and the CUT is only available as a black box.…”
Section: Probabilistic Signature Of a Circuitmentioning
confidence: 99%
“…In traditional equivalence checking [13] both circuits -CUT and the original circuit are available as white box. Hence, it is possible to use techniques like satisfiability solving [14] and randomized structural hashing [15], [16]. In contrast, the problem of trojan detection is more complicated since we only have the original circuit design and the CUT is only available as a black box.…”
Section: Probabilistic Signature Of a Circuitmentioning
confidence: 99%