A register-transfer level testability analyzer

Abstract

This paper presents a statistic-based method to estimate the testability of a design at RegisterTransfer Level. This testability estimation technique is composed of a new proposed high-level design representation and a Monte Carlo simulation which exploits a statistic model to bound the error rate and confidence level of simulation results. The experimental results show that the proposed method can efficiently report more than 60% hard-to-test points of an RL design on average prior to the synthesis task.